参数资料
型号: NCP3125ADR2G
厂商: ON Semiconductor
文件页数: 7/22页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 4A 8SOIC
标准包装: 1
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 5 V
输入电压: 4.5 V ~ 13.2 V
PWM 型: 电压模式
频率 - 开关: 350kHz
电流 - 输出: 4A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 标准包装
供应商设备封装: 8-SOICN
其它名称: NCP3125ADR2GOSDKR
NCP3125
General
The NCP3125 is a PWM synchronous buck regulator
COMP
intended to supply up to a 4 A load for DC ? DC conversion
from 5 V and 12 V buses. The NCP3125 is a regulator that
has integrated high ? side and low ? side NMOSFETs
switches. The output voltage of the converter can be
precisely regulated down to 800 mV ± 1.0% when the VFB
pin is tied to V OUT . The switching frequency is internally set
to 350 kHz. A high gain operational transconductance
amplifier (OTA) is used for voltage mode control of the
Gate Signal
Disable
Enable
2N7002E
power stage.
Duty Ratio and Maximum Pulse Width Limits
Disable
COMP
In steady state DC operation, the duty ratio will stabilize
at an operating point defined by the ratio of the input to the
output voltage. The device can achieve a 75% duty ratio. The
NCP3125 has a preset off ? time of approximately 150 ns,
which ensures that the bootstrap supply is charged every
switching cycle. The preset off time does not interfere with
Base Signal
Enable
MMBT3904
the conversion of 12 V to 0.8 V.
Input Voltage Range (V IN and BST)
The input voltage range for both V IN and BST is 4.5 V to
13.2 V with respect to GND and V SW . Although BST is
rated at 13.2 V with respect to V SW , it can also tolerate
26.5 V with respect to GND.
External Enable/Disable
Once the input voltage has exceeded the boost and UVLO
Figure 15. Recommended Disable Circuits
Power Sequencing
Power sequencing can be achieved with NCP3125 using
two general purpose bipolar junction transistors or
MOSFETs. An example of the power sequencing circuit
using the external components is shown in Figure 16.
threshold at 3 V and V IN threshold at 4 V, the COMP pin
starts to rise. The V SW node is tri ? stated until the COMP
voltage exceeds 0.9 V. Once the 0.9 V threshold is exceeded,
the part starts to switch and the part is considered enabled.
When the COMP pin voltage is pulled below the 400 mV
VSW
NCP3125
FB1
COMP
1.0V
VIN
VSW
NCP3125
FB1
COMP
3.3 V
threshold, it disables the PWM logic, the top MOSFET is
driven off, and the bottom MOSFET is driven on. In the
disabled mode, the OTA output source current is reduced to
10 m A.
When disabling the NCP3125 using the COMP / Disable
pin, an open collector or open drain drive should be used as
shown in Figure 15:
Figure 16. Power Sequencing
Input Voltage Shutdown Behavior
Input voltage shutdown occurs when the IC stops
switching because the input supply reaches UVLO
threshold. Undervoltage Lockout (UVLO) is provided to
ensure that unexpected behavior does not occur when VCC
is too low to support the internal rails and power the
converter. The UVLO is set to permit operation when
converting from an input voltage of 5 V. If the UVLO is
tripped, switching stops, the internal SS is discharged, and
all MOSFET gates are driven low. The V SW node enters a
high impedance state and the output capacitors discharge
through the load with no ringing on the output voltage.
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