参数资料
| 型号： | NCP3126ADR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 18/23页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 3A 8SOIC |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调至 0.8V |
| 输入电压： | 4.5 V ~ 13.2 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 350kHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 标准包装 |
| 供应商设备封装： | 8-SOICN |
| 其它名称： | NCP3126ADR2GOSDKR |
NCP3126
Assuming an output capacitance of 470 m F in parallel with
22 m F with a crossover frequency of 35 kHz, the
compensation values for common output voltages can be
calculated as shown in Table 6:
Table 6. COMPENSATION VALUES
C P
C C
D
I SS
t SS
V ramp
= Compensation pole capacitor
= Compensation capacitor
= Duty ratio
= Soft ? start current
= Soft ? start interval
= Peak ? to ? peak voltage of the ramp
V in
(V)
12
12
12
12
12
12
12
12
12
5
5
5
5
5
5
5
V out
(V)
0.8
1.0
1.1
1.2
1.5
1.8
2.5
3.3
5.0
0.8
1.0
1.1
1.2
1.5
1.8
2.5
L out
( m F)
3.3
3.3
3.3
4.7
4.7
6.8
6.8
8.2
10
3.3
3.3
3.3
4.7
4.7
4.7
4.7
Cf
(nF)
NI
0.180
0.180
0.180
0.180
0.180
0.220
0.220
0.220
NI
0.180
0.180
0.180
0.180
0.180
0.180
Cc
(nF)
180
120
120
120
120
100
100
100
100
100
82
82
82
82
82
82
Rc
(k W )
0.357
0.442
0.475
0.787
0.909
1.5
1.87
2.05
2.5
0.887
1.1
1.65
1.82
2.21
2.61
3.4
Cp
(nF)
2.7
2.7
2.2
2.2
1.8
1.2
1
1
1.2
1.8
1.5
0.82
0.82
0.82
0.82
0.82
V
900 mV
Vcomp
Vout
Figure 25. Soft ? Start Ramp
The delay from the charging of the compensation network
to the bottom of the ramp is considered t ssdelay . The total
delay time is the addition of the current set delay and t ssdelay ,
which in this case is 9 ms and 7.45 ms respectively, for a
total of 16.45 ms.
Calculating Input Inrush Current
The input inrush current has two distinct stages: input
charging and output charging. The input charging of a buck
Calculating Soft ? Start Time
To calculate the soft ? start delay and soft ? start time, the
following equations can be used.
stage is usually not controlled, and is limited only by the
input RC network, and the output impedance of the upstream
power stage. If the upstream power stage is a perfect voltage
source, then the input charge inrush current can be depicted
t SSdelay +
C P ) C C 0.9 V
I SS
2.83 nF ) 80 nF
7.45 ms +
10 m A
3
0.9 V
(eq. 45)
as shown in Figure 26 and calculated as:
IPK
C P = Compensation pole capacitor
C C = Compensation capacitor
I SS = Soft ? start current
The time the output voltage takes to increase from 0 V to
Figure 26. Input Charge Inrush Current
I SS
120 A +
a regulated output voltage is t ss as shown in Equation 46:
C P ) C C D V ramp
t SS +
(eq. 46)
2.83 nF ) 80 nF 27.5% 1.1 V
2.51 ms +
10 m A
I ICinrush_PK 1 +
12
0.1
V IN
CIN ESR
(eq. 47)
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