参数资料
| 型号： | NCP3126ADR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 8/23页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 3A 8SOIC |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调至 0.8V |
| 输入电压： | 4.5 V ~ 13.2 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 350kHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 标准包装 |
| 供应商设备封装： | 8-SOICN |
| 其它名称： | NCP3126ADR2GOSDKR |
NCP3126
Overcurrent Threshold Setting
NCP3126 overcurrent threshold can be set from 50 mV to
0.9 V
COMP
BG
TG
550 mV, by adding a resistor (R SET ) between ISET and
GND. During a short period of time following V IN rising
over UVLO threshold, an internal 10 m A current (I OCSET ) is
sourced from the ISET pin, creating a voltage drop across
R SET . The voltage drop is compared against a stepped
internal voltage ramp. Once the internal stepped voltage
reaches the R SET voltage, the value is stored internally until
power is cycled. The overall time length for the OC setting
procedure is approximately 9 ms. Connecting an R SET
resistor between ISET and GND, the programmed threshold
will be:
Figure 17. Enable/Disable Driver State Diagram
External Soft ? Start
I OCth +
I OCSET * R SET
R DS(on)
3 3.2 A +
10 m A * 24 k W
75 m W
(eq. 1)
The NCP3126 features an external soft ? start function,
which reduces inrush current and overshoot of the output
voltage. Soft ? start is achieved by using the internal current
source of 10.5 m A (typ), which charges the external
integrator capacitor of the OTA. Figure 18 is a typical
soft ? start sequence. The sequence begins once V IN and
V BST surpass their UVLO thresholds and OCP
programming is complete. The current sourced out of the
COMP pin continually increases the voltage until regulation
is reached. Once the voltage reaches 400 mV logic is
enabled. When the voltage exceeds 900 mV, switching
begins. Current is sourced out of the COMP pin, placing the
regulator into open loop operation until 800 mV is sensed at
the FB pin. Once 800 mV is sensed at the FB pin, open loop
operation ends and closed loop operation begins. In closed
loop operation, the OTA is capable of sourcing and sinking
120 m A.
I OCSET = Sourced current
I OCth = Current trip threshold
R DS(on) = On resistance of the low side MOSFET
R SET = Current set resistor
The R SET values range from 5 k W to 55 k W . If R SET is not
connected, the device switches the OCP threshold to a fixed
375 mV value, an internal safety clamp on ISET is triggered
as soon as ISET voltage reaches 700 mV, enabling the
375 mV fixed threshold and ending the OCP setting period.
The current trip threshold tolerance is $ 25 mV. The
accuracy is best at the highest set point (550 mV). The
accuracy will decrease as the set point decreases. MOSFET
tolerances with temperature and input voltage will vary the
over current set threshold operating point. A graph of the
typical current limit set thresholds at 4.5 V and 12 V is
shown in Figure 19.
VCC
COMP
4.2 V
0.9 V
3.85 V
7
6.5
6
5.5
5
VFB
BG
4.5
4
3.5
3
12 V
5.0 V
500 mV
50 mV
TG
BG Comparator
DAC Voltage
BG Comparator Output
Vout
UVLO POR Current Soft ? Start Normal Operation
Delay Trip Set COMP
Delay
UVLO
2.5
2
1.5
1
5
10 15 20 25 30 35 40 45 50
R SET (k W )
Figure 19. R SET Value for Output Current
55
Figure 18. Soft ? Start Sequence
http://onsemi.com
8
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