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参数资料
| 型号： | NCP367OPMUEOTBG |
| 厂商： | ON Semiconductor |
| 文件页数： | 10/13页 |
| 文件大小： | 0K |
| 描述： | IC VOLT PROTECTION OCP OVP 8DFN |
| 标准包装： | 3,000 |
| 应用： | 手持/移动设备 |
| 输入电压： | 1.2 V ~ 28 V |
| 电源电压： | 1.2 V ~ 28 V |
| 电流 - 电源： | 42µA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-VFDFN 裸露焊盘 |
| 供应商设备封装： | 8-DFN（2x2.2） |
| 包装： | 带卷 (TR) |
NCP367
to this option, both fast charge or USB charge are
authorized with the same device.
1500
R LIM (k W ) = 249 / I OCP ? 165
NCP367OxMUxxTBG
R LIM (k W ) = 532 / I OCP ? 180
During overcurrent event, charge area is opened and
FLAG output is tied to low, allowing the m Controller to take
into account the fault event and then open the charge path.
At power up (accessory is plugged on input pins), the
1000
500
GS = Low
GS = High
current is limited up to I LIM during 1.8 ms (typical), to
allow capacitor charge and limit inrush current. If the I LIM
threshold is exceeded over 1.8 ms, the device enter in OCP
burst mode until the overcurrent event disappears.
V BAT Sense
The connection of the V BAT pin to the positive
connection of the Li ion battery pack allows preventing
overvoltage transient, greater than 4.35 V. In case of wrong
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400 500
600
700
800
0
Rilim(k W )
Figure 12. I OCP versus R LIM , GS = low and high,
1.5 A version
3
charger conditions, the PMOS is then opened, eliminating
Battery pack over voltage which could create safety issues
and temperature increasing.
The 4.35 V comparator has a 150 mV built ? in hysteresis.
More of that, deglitch function of 2 ms is integrated to
prevent voltage transients on the Battery voltage. If the
battery over voltage condition exceeds deglitch time, the
charge path is opened and FLAG pin is tied to low level
until the V BAT is greater than 4.35 V – hysteresis.
At wall adapter insertion, and if the battery is fully
2
GS = Low
charged, V bat comparator stays locked until battery needs
to be recharged (4.2 V typ ? 4.1 V min).
A serial resistor has to be placed in series with Vbat pin
1
GS = High
and battery connection, with a 200 k W recommended
value.
PCB Recommendations
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800
The NCP367 integrates low R DS(on) PMOS FET,
nevertheless PCB layout rules must be respected to
Rilim (k W )
Figure 13. Over Current Threshold versus
R LIMIT 2.85 A Version
Typical R LIM calculation is following:
NCP367DxMUxxTBG
properly evacuate the heat out of the silicon. The DFN
PAD1 corresponds to the PMOS drain so must be connected
to OUT plane to increase the heat transfer. Of course, in any
case, this pad shall be not connected to any other potential.
Following figure shows package thermal resistance of a
DFN 2.2x2 mm.
http://onsemi.com
10
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