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| 型号： | NCP5104PG |
| 厂商： | ON Semiconductor |
| 文件页数： | 4/15页 |
| 文件大小： | 0K |
| 描述： | IC DRIVER HALF BRIDGE HV 8-DIP |
| 标准包装： | 50 |
| 配置： | 半桥 |
| 输入类型： | 非反相 |
| 延迟时间： | 620ns |
| 电流 - 峰： | 250mA |
| 配置数： | 1 |
| 输出数： | 2 |
| 高端电压 - 最大（自引导启动）： | 600V |
| 电源电压： | 10 V ~ 20 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
| 产品目录页面： | 1127 (CN2011-ZH PDF) |
| 其它名称： | NCP5104PG-ND NCP5104PGOS |
NCP5104
ELECTRICAL CHARACTERISTIC (V CC = V boot = 15 V, V GND = V bridge , ? 40 ° C < T J < 12 5 ° C, Outputs loaded with 1 nF)
T J ? 40 ° C to 125 ° C
Rating
Symbol
Min
Typ
Max
Units
OUTPUT SECTION
Output high short circuit pulsed current V DRV = 0 V, PW v 10 m s (Note 1)
Output low short circuit pulsed current V DRV = Vcc, PW v 10 m s (Note 1)
Output resistor (Typical value @ 25 ° C) Source
Output resistor (Typical value @ 25 ° C) Sink
High level output voltage, V BIAS ? V DRV_XX @ I DRV_XX = 20 mA
Low level output voltage V DRV_XX @ I DRV_XX = 20 mA
I DRVsource
I DRVsink
R OH
R OL
V DRV_H
V DRV_L
?
?
?
?
?
?
250
500
30
10
0.7
0.2
?
?
60
20
1.6
0.6
mA
mA
W
W
V
V
DYNAMIC OUTPUT SECTION
Turn ? on propagation delay (Vbridge = 0 V) (Note 2)
Turn ? off propagation delay (Vbridge = 0 V or 50 V) (Note 3)
Shutdown propagation delay, when Shutdown is enabled
Shutdown propagation delay, when Shutdown is disabled
Output voltage rise time (from 10% to 90% @ V CC = 15 V) with 1 nF load
Output voltage fall time (from 90% to 10% @ V CC = 15 V) with 1 nF load
Propagation delay matching between the High side and the Low side
@ 25 ° C (Note 4)
Internal fixed dead time (Note 5)
t ON
t OFF
t sd_en
t sd_dis
t r
t f
D t
DT
?
?
?
?
?
?
?
400
620
100
100
620
85
35
10
520
800
170
170
800
160
75
45
650
ns
ns
ns
ns
ns
ns
ns
ns
INPUT SECTION
Low level input voltage threshold
Input pull ? down resistor (V IN < 0.5 V)
High level input voltage threshold
Logic “1” input bias current @ V IN = 5 V @ 25 ° C
Logic “0” input bias current @ V IN = 0 V @ 25 ° C
V IN
R IN
V IN
I IN+
I IN ?
?
?
2.3
?
?
?
200
?
5
?
0.8
?
?
25
2.0
V
k W
V
m A
m A
SUPPLY SECTION
Vcc UV Start ? up voltage threshold
Vcc UV Shut ? down voltage threshold
Hysteresis on Vcc
Vboot Start ? up voltage threshold reference to bridge pin
Vcc_stup
Vcc_shtdwn
Vcc_hyst
Vboot_stup
8.0
7.3
0.3
8.0
8.9
8.2
0.7
8.9
9.8
9.0
?
9.8
V
V
V
V
(Vboot_stup = Vboot ? Vbridge)
Vboot UV Shut ? down voltage threshold
Hysteresis on Vboot
Leakage current on high voltage pins to GND
(V BOOT = V BRIDGE = DRV_HI = 600 V)
Consumption in active mode (Vcc = Vboot, fsw = 100 kHz and 1 nF load on
both driver outputs)
Consumption in inhibition mode (Vcc = Vboot)
Vcc current consumption in inhibition mode
Vboot current consumption in inhibition mode
Vboot_shtdwn
Vboot_shtdwn
I HV_LEAK
ICC1
ICC2
ICC3
ICC4
7.3
0.3
?
?
?
?
?
8.2
0.7
5
4
250
200
50
9.0
?
40
5
400
?
?
V
V
m A
mA
m A
m A
m A
1.
2.
3.
4.
5.
Parameter guaranteed by design.
T ON = T OFF + DT
Turn ? off propagation delay @ Vbridge = 600 V is guaranteed by design.
See characterization curve for D t parameters variation on the full range temperature.
Timing diagram definition see: Figure 4, Figure 5 and Figure 6.
http://onsemi.com
4
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