参数资料
型号: NCP5217AMNTXG
厂商: ON Semiconductor
文件页数: 9/16页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 14-QFN
标准包装: 3,000
PWM 型: 电流/电压模式
输出数: 1
频率 - 最大: 330kHz
电源电压: 4.5 V ~ 27 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 14-VFQFN 裸露焊盘
包装: 带卷 (TR)
其它名称: NCP5217AMNTXG-ND
NCP5217AMNTXGOSTR
NCP5217A
DETAILED OPERATING DESCRIPTION
General
The NCP5217A synchronous step ? down power
controller contains a PWM controller for wide
battery/adaptor voltage range applications
The NCP5217A includes power good voltage monitor,
soft ? start, over current protection, under ? voltage
protection, overvoltage protection and thermal shutdown.
further improve transient response in CCM, a transient
response enhancement circuitry is implemented inside the
NCP5217A. In CCM operation, the controller is
continuously monitoring the COMP pin output voltage of
the error amplifier to detect the load transient events. The
functional block diagram of TRE is shown below.
The NCP5217A features power saving function which can
increase the efficiency at light load. It is ideal for battery
operated systems. The IC is packaged in QFN14.
COMP
R
+
+
TRE
Control Logic
The internal control logic is powered by V CC . The device
is controlled by an EN_SKIP pin. The EN_SKIP serves two
functions. When voltage of EN_SKIP is below
VEN_Disable, it shuts down the device. When the voltage
of EN_SKIP is between VEN_FPWM and VEN_SKIP, the
device is operating as force PWM mode. When voltage level
of EN_SKIP is above VEN_SKIP, the device is operating as
power saving mode. When EN_SKIP is above
VEN_Disable, the internal Vref is activated and power ? on
reset occurs which resets all the protection faults. Once Vref
reaches its regulation voltage, an internal signal will wake
up the supply under ? voltage monitor which will assert a
“GOOD” condition. In addition, the NCP5217A
continuously monitors V CC level with an undervoltage
lockout (UVLO) function.
Forced PWM Operation (FPWM Mode)
The device is operating as force PWM mode if EN_SKIP
voltage keeps at between VEN_FPWM and VEN_SKIP.
Under this mode, the low ? side gate driver signal is forced to
be the complement of the high ? side gate driver signal. This
mode allows reverse inductor current, in such a way that it
provides more accurate voltage regulation and better (fast)
transient response. During the soft ? start operation, the
NCP5217A automatically runs as FPWM mode regardless
of the EN_SKIP setting at either FPWM or SKIP mode to
make sure to have smooth power up.
Pulse Skipping Operation (Skip Mode)
The device is operating as skip mode if EN_SKIP voltage
keeps above VEN_SKIP. However, in medium and high
load range, the controller still runs in
continuous ? conduction ? mode (CCM) of which it behaves
exactly same as FPWM mode. In light load range, the
controller will go to skip mode which is similar to
conventional constant on ? time scheme.
C
internal TRE_TH
Figure 14. Block Diagram of TRE Circuit
Once the large transient occurs, the COMP signal may be
large enough to exceed the threshold and then TRE “flag”
signal will be asserted in a short period which is typically
around one normal switching cycle. In this short period, the
controller will be running at high frequency and hence has
faster response. After that the controller comes back to
normal switching frequency operation. We can program the
internal TRE threshold (TRE_TH). For detail please see the
electrical table of “TRE Setting” section. Basically, the
recommend internal TRE threshold value is around 1.5
times of peak ? to ? peak value of the COMP signal at CCM
operation. The higher the internal TRE_TH, the lower
sensitivity to load transient. The TRE function can be
disable by setting the Rtre which is connecting to DL/TRE
pin to less than 25 k W . For system component saving, it is
usually set as default value, that is, Rtre is open ( w 75 k W )
and internal TRE_TH is 300 mV typical.
Top to Bottom SWN, V o , Transient Signal
Figure 15. Transient Response with TRE Disable
Transient Response Enhancement (TRE)
For the conventional PWM controller in CCM, the fastest
response time is one switching cycle in the worst case. To
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