参数资料
| 型号： | NCP5222MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 10/28页 |
| 文件大小： | 0K |
| 描述： | IC CTLR BUCK 2CH 2PH 28QFN |
| 标准包装： | 4,000 |
| 应用： | 多相控制器 |
| 电流 - 电源： | 2.5mA |
| 电源电压： | 4.5 V ~ 27 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VFQFN 裸露焊盘 |
| 供应商设备封装： | 28-QFN（4x4） |
| 包装： | 带卷 (TR) |
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NCP5222
General
The NCP5222, a fast ? transient ? response and
high ? efficiency dual ? channel / two ? phase buck controller
with builtin gate drivers, provides multifunctional power
solutions for notebook power system. 180 ° interleaved
operation between the two channels / phases has a capability
of reducing cost of the common input capacitors and
improving noise immunity. The interleaved operation also
can reduce cost of the output capacitors with the two ? phase
configuration. Input supply voltage feedforward control is
employed to deal with wide input voltage range. On ? line
programmable and automatic power ? saving control ensures
high efficiency over entire load range. Fast transient
response reduces requirement on the output filters. In the
dual ? channel operation mode, the two output power rails are
regulated individually. In the two ? phase operation mode,
the two output power rails are connected together by an
external switch and current ? sharing control is enabled to
balance power delivery between phases.
Dual ? Channel Mode or Two ? Phase Mode
The NCP5222 can be externally configured to be working
in dual ? channel operation mode or two ? phase operation
mode. In the dual ? channel operation mode, the two output
power rails are regulated individually. In the two ? phase
operation mode, the two output power rails are connected
together by an external switch and current ? sharing control
is enabled to balance power delivery between phases.
Figure 5 shows two typical external configurations. In
Figure 5(a), the controller is configured to operate in the
dual ? channel mode by connecting the pin DRVS with the
pin V CCP . In Figure 5(b), the controller is configured to
operate in the two ? phase mode. In this mode, an external
MOSFET SSH is employed to connect the two output power
rails together, and the pin DRVS of the NCP5222 provides
driving signal to SSH. Two filter capacitors CCS1 and
CICS2 are connected with two current ? sense output pins
ICS1 and ICS2, respectively. A typical timing diagram is
shown in Figure 6.
C ICS2
C I CS1
7
1
7
1
NCP5222
18 19
S SH
Vo2
NCP5222
18 19
S SH
Vo1
( a ) Dual ? C hannel
( b ) Two ? Phas e
Figure 5. Mode Configurations
Mode Detection
In the initial stage of the IC powering up, there is mode
detection period to read the external setup just after V IN and
V CC are both ready and at least one of ENs is enabled. In
Figure 6, V IN and V CC are powered up first. At 3.5 us after
EN2 goes high, a 53 m s mode detection period starts. The
DRVS pin is pulled down by an internal 2 k W . At the end of
the mode detection, if the DRVS is higher than V CCP ? 0.5 V
the system goes to the dual ? channel mode and leaves DRVS
high impedance. If the DRVS is lower than V CCP ? 0.5 V, the
system goes to the two ? phase mode and the DRVS pin is
pulled down to PGND1 by an internal 10 W FET.
DRVS Softstart in Two ? Phase Mode
In the two ? phase mode, the DRVS softstart begins after
the both PGOOD1 and PGOOD2 become valid. During the
DRVS softstart, 1 mA current is sourced out from the DRVS
pin and thus voltage in DRVS is ramping up. The DRVS
soft ? start is complete after the DRVS voltage is higher than
V CCP ? 0.2 V, and then the DRVS pin is pulled up to V CCP
by an internal 20 W FET.
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