参数资料
| 型号： | NCP5222MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 15/28页 |
| 文件大小： | 0K |
| 描述： | IC CTLR BUCK 2CH 2PH 28QFN |
| 标准包装： | 4,000 |
| 应用： | 多相控制器 |
| 电流 - 电源： | 2.5mA |
| 电源电压： | 4.5 V ~ 27 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VFQFN 裸露焊盘 |
| 供应商设备封装： | 28-QFN（4x4） |
| 包装： | 带卷 (TR) |
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NCP5222
I OC1 + I O1max )
I OC2 + I O2max )
load transient occurs, the COMP signal is possible to exceed
the threshold and then TRE is tripped in a short period,
which is typically around one normal switching cycle. In this
short period, the controller runs at higher frequency and
therefore has faster response. After that the controller comes
back to normal operation.
Protection Funtions
The NCP5222 provides comprehensive protection
functions for the power system, which include input power
supply undervoltage lock out, output overcurrent protection,
output overvoltage protection, output undervoltage
protection, and thermal shutdown protection. The priority of
the protections from high to low as: 1. Thermal protection
and input power supply undervoltage lockout; 2. Output
overvoltage protection; 3. Output overcurrent protection
and output undervoltage protection.
Input Power Supply Undervoltage Lock Out (UVLO)
The NCP5222 provides UVLO functions for both input
power supplies (V IN and V CC ) of the power stage and
controller itself. The two UVLO functions make it possible
to have flexible power sequence between V IN and V CC for
the power systems. The start threshold of V IN is 3.6 V, and
the starting threshold of V CC is 4.25 V.
so that the overcurrent threshold I OC is the maximum
loading current I Omax per channel.
I OC1 + I O1max (eq. 27)
I OC2 + I O2max (eq. 28)
In two ? phase operation mode, to make sure the OCP is not
triggered in the normal operation, the worst case need to be
considered, in which the maximum load step in one power
rail comes just after the two phases are sharing the maximum
load from the other power rail. In this case, the two
overcurrent thresholds need to be set as
DCR 2 @ k CS2
(eq. 29)
DCR 1 @ k CS1 ) DCR 2 @ k CS2
and
DCR 1 @ k CS1
(eq. 30)
DCR 1 @ k CS1 ) DCR 2 @ k CS2
The both phases also has the same internal overcurrent
current ? sense threshold V TH_OC = 30 mV, that means
I OC1 @ DCR 1 @ k CS1 + I OC2 @ DCR 2 @ k CS2 + V TH_OC
(eq. 31)
Use of Equations 29, 30, and 31 leads to:
Output Overcurrent Protection (OCP)
The NCP5222 protects converter if overcurrent occurs.
The current through each channel is continuously monitored
with differential current sense. If inductor current exceeds
the current threshold, the high ? side gate drive will be turned
I OC1 + I O1max @ 1 )
I OC2 + I O2max @ 1 )
I O2max
I O1max ) I O2max
I O1max
I O1max ) I O2max
(eq. 32)
(eq. 33)
I OC(Peak) +
I OC + I OC(Peak) *
off cycle ? by ? cycle. In the meanwhile, an internal OC fault
timer will be triggered. If the fault still exists after about
53 m s, the corresponding channel latches off, both the
high ? side MOSFET and the low ? side MOSFET are turned
off. The fault remains set until the system has shutdown and
re ? applied V CC and/or the enable signal EN has toggled
states.
Current limit threshold V TH_OC between CS+ and CS ? is
internally fixed to 30 mV. The current limit can be
programmed by the inductor ’s DCR and the current ? sense
resistor divider with R CS1 and R CS2 . The inductor peak
current limit is
V TH_OC
(eq. 25)
k CS @ DCR
The DC current limit is
V O @ V IN * V O
(eq. 26)
2 @ V IN @ f SW @ L
where V IN is input supply voltage of the power stage, and
f SW is 300 kHz normal switching frequency.
In the dual ? channel mode, the steady ? state inductor DC
current is equal to output loading current I Omax per channel,
Output Overvoltage Protection (OVP)
An OVP circuit monitors the feedback voltages to prevent
loads from over voltage. OVP limit is typically 115% of the
nominal output voltage level, and the hysteresis of the OV
detection comparator is 5% of the nominal output voltage.
If the OV event lasts less than 1.5 m s, the controller remains
normal operation when the output of the OV comparator is
released, otherwise an OV fault is latched after 1.5 m s. After
the fault is latched, the high ? side MOSFET is latched off and
the low ? side MOSFET will be on and off responding to the
output of the OV detection comparator. The fault remains set
until the system has shutdown and re ? applied V CC and/or
the enable signal EN has toggled states.
Output Undervoltage Protection (UVP)
A UVP circuit monitors the feedback voltages to detect
undervoltage. UVP limit is typically 80% of the nominal
output voltage level. If the output voltage is below this
threshold, a UV fault is set. If an OV protection is set before,
the UV fault will be masked. If no OV protection set, an
internal fault timer will be triggered. If the fault still exists
after about 27 m s, the corresponding channel is latches off,
both the high ? side MOSFET and the low ? side MOSFET are
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