参数资料
| 型号： | NCP5222MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 13/28页 |
| 文件大小： | 0K |
| 描述： | IC CTLR BUCK 2CH 2PH 28QFN |
| 标准包装： | 4,000 |
| 应用： | 多相控制器 |
| 电流 - 电源： | 2.5mA |
| 电源电压： | 4.5 V ~ 27 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VFQFN 裸露焊盘 |
| 供应商设备封装： | 28-QFN（4x4） |
| 包装： | 带卷 (TR) |
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NCP5222
R11
R14
FB1
COMP1
PWM1
SWN1
L1
Vo1
IL1
Io1
0.8V
Rcs11
Ccs1
C1
Rcs12
CS1+
IFB2
ICS1
Rics1
20k
G i
CS1 ?
1.25V
ISH
G m
ICS2
Rics2
20k
G i
CS2 ?
CS2+
Ssh
Rcs22
0.8V
Rcs21
Ccs2
C2
R24
FB2
COMP2
PWM2
SWN2
L2
Vo2
IL2
Io2
R21
Figure 10. PWM Output Regulation in Two ? Phase Mode
In the two ? phase operation, the phase 1 has the same
where
V O1 + 1 ) @ V ref1 + 1 ) @ 0.8 (eq. 6)
output regulation control as what is in the dual ? channel
operation. The output voltage is
R 11 R 11
R 14 R 14
However, in order to achieve current ? sharing function,
V ICS1 + G ICS1 @ R ICS1 @ V CS1 ) V ICS_Offset
+ 10 @ V CS1 ) 1.25
V ICS2 + G ICS2 @ R ICS2 @ V CS2 ) V ICS_Offset
+ 10 @ V CS2 ) 1.25
(eq. 9)
(eq. 10)
V O2 + 1 ) @ V ref2 * I FB2 @ R 21
+ 1x10 ? 3 @ V CS2 * V CS1
k CS1 +
k CS2 +
the output voltage in phase 2 is adjusted to be higher or lower
than V O1 to balance the power delivery in the two phases, by
means of an injection current I FB2 into the phase 2 error
amplifier ’s non ? inverting node. Thus output voltage of the
phase 2 is
R 21
R 24
(eq. 7)
R 21
+ 1 ) @ 0.8 * I FB2 @ R 21
R 24
The injection current I FB2 is proportional to the difference
between the two current ? sense output signals V ICS2 and
V ICS1 , that is
I FB2 + G IFB2 @ V ICS2 * V ICS1
+ 1x10 ? 4 @ V ICS2 * V ICS1
(eq. 8)
V CS1 + k CS1 @ I L1 @ DCR 1 (eq. 11)
V CS2 + k CS2 @ I L2 @ DCR 2 (eq. 12)
and
R CS12
(eq. 13)
R CS11 ) R CS12
R CS22
(eq. 14)
R CS21 ) R CS22
Based on understanding of the power stage connection,
the current distribution in the two phases can be calculated
by
I L1 + I O1 * I Share (eq. 15)
and
I L2 + I O2 * I Share (eq. 16)
+ 1x10 ? 3 @ k CS2 @ DCR 2 @ I L2 * k CS1 @ DCR 1 @ I L1
http://onsemi.com
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