参数资料
型号: NCP5314FTR2G
厂商: ON Semiconductor
文件页数: 20/29页
文件大小: 0K
描述: IC CTLR CPU 2/3/4 PHASE 32-LQFP
产品变化通告: Product Discontinuation 01/Oct/2008
标准包装: 2,000
应用: 控制器,CPU
输入电压: 9.5 V ~ 13.2 V
输出数: 4
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 32-LQFP
供应商设备封装: 32-LQFP(7x7)
包装: 带卷 (TR)
NCP5314
I C,MAX
I C,MIN
Δ I C,IN = I C,MAX ? I C,MIN
inrush currents reduce the expected life of the input
capacitors. The inductor ’s limiting effect on the input
current slew rate becomes increasingly beneficial during
0A
?I IN,AVG
t ON
FET Off,
Caps Charging
T/4
load transients.
The worst case input current slew rate will occur during
the first few PWM cycles immediately after a step?load
change is applied as shown in Figure 25. When the load is
applied, the output voltage is pulled down very quickly.
FET On,
Caps Discharging
Figure 24. Input Capacitor Current for a
Four?Phase Converter
Δ I Lo is the peak?to?peak ripple current in the output
inductor of value Lo:
Current through the output inductors will not change
instantaneously, so the initial transient load current must be
conducted by the output capacitors. The output voltage will
step downward depending on the magnitude of the output
current (I O,MAX ), the per capacitor ESR of the output
capacitors (ESR OUT ) and the number of the output
capacitors (N OUT ) as shown in Figure 25. Assuming the load
current is shared equally between all phases, the output
D ILo + (VIN * VOUT) @ D (Lo @ fSW)
(10)
voltage at full transient load will be:
For the four?phase converter, the input capacitor(s) RMS
VOUT,FULL?LOAD +
(14)
ICIN,RMS + [4D @ (IC,MIN2 ) IC,MIN @ D IC,IN
current is then:
(11)
) D IC,IN2 3) ) IIN,AVG2 @ (1 * 4D)]1 2
Select the number of input capacitors (N IN ) to provide the
VOUT,NO?LOAD * (IO,MAX f ) @ ESROUT NOUT
When the control MOSFET (Q1 in Figure 25) turns ON,
the input voltage will be applied to the opposite terminal of
the output inductor (the SWNODE). At that instant, the
voltage across the output inductor can be calculated as:
NIN + ICIN,RMS IRMS,RATED
RMS input current (I CIN,RMS ) based on the RMS ripple
current rating per capacitor (I RMS,RATED ):
(12)
D VLo + VIN * VOUT,FULL?LOAD
+ VIN * VOUT,NO?LOAD
) (IO,MAX f ) @ ESROUT NOUT
(15)
For a four?phase converter with perfect efficiency ( η = 1),
the worst case input ripple?current will occur when the
converter is operating at a 12.5% duty cycle. At this
operating point, the parallel combination of input capacitors
must support an RMS ripple current equal to 12.5% of the
converter ’s DC output current. At other duty cycles, the
ripple?current will be less. For example, at a duty cycle of
either 6% or 19%, the four?phase input ripple?current will
be approximately 10% of the converter’s DC output current.
In general, capacitor manufacturers require derating to the
specified ripple?current based on the ambient temperature.
More capacitors will be required because of the current
The differential voltage across the output inductor will
cause its current to increase linearly with time. The slew rate
of this current can be calculated from:
dILo dt + D VLo Lo (16)
Current changes slowly in the input inductor so the input
capacitors must initially deliver the vast majority of the
input current. The amount of voltage drop across the input
capacitors ( Δ V Ci ) is determined by the number of input
capacitors (N IN ), their per capacitor ESR (ESR IN ) and the
current in the output inductor according to:
derating. The designer should know the ESR of the input
capacitors. The input capacitor power loss can be calculated
from:
D VCi + ESRIN NIN @ dILo dt @ tON
+ ESRIN NIN @ dILo dt @ D fSW
(17)
PCIN + ICIN,RMS2 @ ESR_per_capacitor NIN (13)
Low ESR capacitors are recommended to minimize losses
and reduce capacitor heating. The life of an electrolytic
capacitor is reduced 50% for every 10 ° C rise in the
capacitor ’s temperature.
Before the load is applied, the voltage across the input
inductor (V Li ) is very small and the input capacitors charge
to the input voltage V IN . After the load is applied, the voltage
drop across the input capacitors, Δ V Ci , appears across the
input inductor as well. Knowing this, the minimum value of
the input inductor can be calculated from:
5. Input Inductor Selection
The use of an inductor between the input capacitors and
the power source will accomplish two objectives. First, it
LiMIN + VLi
+ D VCi
dIIN dtMAX
dIIN dtMAX
(18)
will isolate the voltage source and the system from the noise
generated in the switching supply. Second, it will limit the
dI IN /dt MAX is the maximum allowable input current slew
rate.
inrush current into the input capacitors at power up. Large
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20
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