参数资料
| 型号： | NCP5314FTR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 25/29页 |
| 文件大小： | 0K |
| 描述： | IC CTLR CPU 2/3/4 PHASE 32-LQFP |
| 产品变化通告： | Product Discontinuation 01/Oct/2008 |
| 标准包装： | 2,000 |
| 应用： | 控制器，CPU |
| 输入电压： | 9.5 V ~ 13.2 V |
| 输出数： | 4 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 带卷 (TR) |
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NCP5314
9. Error Amplifier Tuning
After the steady?state (static) AVP has been set and the
current sense network has been optimized, the Error
Amplifier must be tuned. The gain of the Error Amplifier
should be adjusted to provide an acceptable transient
response by increasing or decreasing the Error Amplifier ’s
feedback capacitor (C AMP in the Applications Diagram).
The bandwidth of the control loop will vary directly with the
gain of the error amplifier.
If C AMP is too large, the loop gain/bandwidth will be low,
the COMP pin will slew too slowly and the output voltage
will overshoot as shown in Figure 33. On the other hand, if
C AMP is too small, the loop gain/bandwidth will be high, the
COMP pin will slew very quickly and overshoot will occur.
Integrator “wind up” is the cause of the overshoot. In this
Figure 33. The Value of C AMP Is Too High and the
Loop Gain/Bandwidth Too Low. COMP Slews Too
Slowly Which Results in Overshoot in V OUT .
Figure 35. The Value of C AMP Is Optimal. COMP Slews
Quickly Without Spiking or Ringing. V OUT Does Not
Overshoot and Monotonically Settles to Its Final Value.
case, the output voltage will transition more slowly because
COMP spikes upward as shown in Figure 34. Too much loop
gain/bandwidth increases the risk of instability. In general,
one should use the lowest loop gain/bandwidth possible to
achieve acceptable transient response. This will insure good
stability. If C AMP is optimal, the COMP pin will slew
quickly but not overshoot and the output voltage will
monotonically settle as shown in Figure 35.
After the control loop is tuned to provide an acceptable
transient response, the steady?state voltage ripple on the
COMP pin should be examined. When the converter is
operating at full steady?state load, the peak?to?peak voltage
ripple (V PP ) on the COMP pin should be less than 20 mV PP
as shown in Figure 36. Less than 10 mV PP is ideal. Excessive
ripple on the COMP pin will contribute to jitter.
Figure 34. The Value of C AMP Is Too Low and the
Loop Gain/Bandwidth Too High. COMP Moves Too
Quickly, Which Is Evident from the Small Spike in Its
Voltage When the Load Is Applied or Removed. The
Output Voltage Transitions More Slowly Because of
the COMP Spike.
Figure 36. At Full?Load the Peak?to?Peak Voltage
Ripple on the COMP Pin Should Be Less than 20 mV
for a Well?Tuned/Stable Controller. Higher COMP
Voltage Ripple Will Contribute to Output Voltage Jitter.
http://onsemi.com
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