参数资料
| 型号： | NCP5314FTR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 21/29页 |
| 文件大小： | 0K |
| 描述： | IC CTLR CPU 2/3/4 PHASE 32-LQFP |
| 产品变化通告： | Product Discontinuation 01/Oct/2008 |
| 标准包装： | 2,000 |
| 应用： | 控制器，CPU |
| 输入电压： | 9.5 V ~ 13.2 V |
| 输出数： | 4 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 带卷 (TR) |
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NCP5314
The input inductance value calculated from Equation 18
is relatively conservative. It assumes the supply voltage is
very “stiff” and does not account for any parasitic elements
that will limit dI/dt such as stray inductance. Also, the ESR
values of the capacitors specified by the manufacturer’s data
sheets are worst case high limits. In reality, input voltage
“sag,” lower capacitor ESRs and stray inductance will help
reduce the slew rate of the input current.
As with the output inductor, the input inductor must
support the maximum current without saturating the
inductor. Also, for an inexpensive iron powder core, such as
the ?26 or ?52 from Micrometals, the inductance “swing”
with DC bias must be taken into account and inductance will
decrease as the DC input current increases. At the maximum
input current, the inductance must not decrease below the
minimum value or the dI/dt will be higher than expected.
MAX dI/dt occurs in
first few PWM cycles.
6. MOSFET and Heatsink Selection
Power dissipation, package size and thermal requirements
drive MOSFET selection. To adequately size the heat sink,
the design must first predict the MOSFET power
dissipation. Once the dissipation is known, the heat sink
thermal impedance can be calculated to prevent the
specified maximum case or junction temperatures from
being exceeded at the highest ambient temperature. Power
dissipation has two primary contributors: conduction losses
and switching losses. The control or upper MOSFET will
display both switching and conduction losses. The
synchronous or lower MOSFET will exhibit only
conduction losses because it switches into nearly zero
voltage. However, the body diode in the synchronous
MOSFET will suffer diode losses during the non?overlap
time of the gate drivers.
V OUT
I Li
Vi(t = 0) = 12 V
Q1
SWNODE
I Lo
Vo(t = 0) = 1.745 V
Li
TBD
Lo
+ Vi
? 12 V
N Ci × Ci
+ V Ci
Q2
+
N Co × Co
14 u(t)
ESR Ci /N Ci
ESR Co /N Co
Figure 25. Calculating the Input Inductance
For the upper or control MOSFET, the power dissipation
I D
can be approximated from:
PD,CONTROL + (IRMS,CNTL2 @ RDS(on))
(19)
V GS_TH
V GATE
) (ILo,MAX @ Qswitch Ig @ VIN @ fSW)
) (Qoss 2 @ VIN @ fSW) ) (VIN @ QRR @ fSW)
The first term represents the conduction or IR losses when
the MOSFET is ON while the second term represents the
switching losses. The third term is the loss associated with
the control and synchronous MOSFET output charge when
Q GS1
Q GS2
Q GD
V DRAIN
the control MOSFET turns ON. The output losses are caused
by both the control and synchronous MOSFET but are
Figure 26. MOSFET Switching Characteristics
dissipated only in the control FET. The fourth term is the loss
due to the reverse recovery time of the body diode in the
synchronous MOSFET. The first two terms are usually
adequate to predict the majority of the losses.
http://onsemi.com
21
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