参数资料
| 型号： | NCP5318FTR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 25/32页 |
| 文件大小： | 0K |
| 描述： | IC CTLR CPU 2/3/4 PHASE 32-LQFP |
| 产品变化通告： | Product Obsolescence 11/Feb/2009 |
| 标准包装： | 2,000 |
| 应用： | 控制器，CPU |
| 输入电压： | 9.5 V ~ 13.2 V |
| 输出数： | 4 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 带卷 (TR) |
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NCP5318
I RMS,CNTL is the RMS value of the current in the control
MOSFET:
The first term represents the conduction or I 2 R losses
when the MOSFET is ON and the second term represents the
ILo,MIN ) Lo,MIN ))1 2
IRMS,CNTL + (D
(ILo,MAX2 * ILo,MAX
3
I 2
(eq. 21)
diode losses that occur during the gate non ? overlap time.
All terms were defined in the previous discussion for the
control MOSFET with the exception of:
ILo,MAX + O,MAX ) D ILo
I
ILo,MIN ) Lo,MIN ))1 2
I Lo,MAX is the maximum output inductor current:
(eq. 22)
f 2
I Lo,MIN is the minimum output inductor current:
IRMS,SYNCH + ((1 * D)
(ILo,MAX2 ) ILo,MAX
3
I 2
(eq. 28)
ILo,MIN + O,MAX * D ILo
I
f 2
(eq. 23)
I D
D + VOUT (eq. 24)
D
D ILo + (VIN * VOUT)
Qswitch + Qgs2 ) Qgd
PD,SYNCH + (IRMS,SYNCH2
RDS(on))
q T t (TJ * TA) PD
I O,MAX is the maximum converter output current.
D is the duty cycle of the converter:
VIN
D I Lo is the peak ? to ? peak ripple current in the output
inductor of value L o :
(eq. 25)
(Lo fSW)
R DS(on) is the ON resistance of the high side MOSFET at
the applied gate drive voltage. Q switch is the post gate
threshold portion of the gate ? to ? source charge plus the
gate ? to ? drain charge. This may be specified in the data sheet
or approximated from the gate ? charge curve as shown in the
Figure 25.
(eq. 26)
I g is the output current from the gate driver IC.
V IN is the input voltage to the converter.
f sw is the switching frequency of the converter.
Q RR is the reverse recovery charge of the lower
MOSFET.
Q oss is the sum of the high and low side MOSFET
output charges specified in the data sheets, or
estimated from integrating C OSS from zero volts to
V IN .
For the lower or synchronous MOSFET, the power
dissipation can be approximated from:
(eq. 27)
) (Vfdiode IO,MAX tnonoverlap fSW)
where:
Vf diode is the forward voltage of the MOSFET’s
intrinsic diode at the converter output current.
V GATE
V GS_TH
Q GS1 Q GS2 Q GD V DRAIN
Figure 25. MOSFET Switching Characteristics
When the MOSFET power dissipations are known, the
designer can calculate the required thermal impedance to
maintain a specified junction temperature at the worst case
ambient operating temperature.
(eq. 29)
where:
q T is the total thermal impedance ( q JC + q SA );
q JC is the junction ? to ? case thermal impedance of the
MOSFET;
q SA is the sink ? to ? ambient thermal impedance of
the heatsink assuming direct mounting of the
MOSFET if no thermal “pad” is used;
T J is the specified maximum allowed junction
temperature;
T A is the worst case ambient operating temperature.
For TO ? 220 and TO ? 263 packages, standard FR ? 4
copper clad circuit boards will have approximate thermal
resistances ( q SA ) as shown below:
Pad Size (in 2 /mm 2 ) Single ? Sided 1 oz. Copper
0.50/323 60 ? 65 ° C/W
t nonoverlap is the non ? overlap time between the upper
and lower gate drivers to prevent cross conduction.
This time is usually specified in the data sheet for the
driver IC.
http://onsemi.com
25
0.75/484
1.00/645
1.50/968
55 ? 60 ° C/W
50 ? 55 ° C/W
45 ? 50 ° C/W
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