参数资料
型号: NCP5386BMNR2G
厂商: ON Semiconductor
文件页数: 27/33页
文件大小: 0K
描述: IC CTLR BUCK 1/2PHASE 32-QFN
标准包装: 2,500
应用: 控制器,Intel VR10、VR11、AMD CPU
输入电压: 4.75 V ~ 5.25 V
输出数: 2
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN(5x5)
包装: 带卷 (TR)
NCP5386, NCP5386A, NCP5386B
Dynamic VID Testing
The V TT tool provides for VID stepping based on the
Intel Requirements. Select the Dynamic VID option.
Before enabling the test set the lowest VID to 0.5 V or
greater and set the highest VID to a value that is greater than
the lowest VID selection, then enable the test. See
Figures 25 through 27.
Design Methodology
Decoupling the V CC Pin on the IC
An RC input filter is required as shown in the V CC pin to
minimize supply noise on the IC. The resistor should be
sized such that it does not generate a large voltage drop
between the 12 V supply and the IC. See the schematic
values.
Understanding Soft ? Start
The controller supports two different startup routines. An
AMD ramp to the initial VID code, or a VR11 Ramp to the
1.1 V VID code, with a pause to capture the VID code then
resume ramping to target value based on an internal slew
rate limit. See Figures 28 and 29. The controller is designed
to regulate to the voltage on the SS pin until it reaches the
internal DAC voltage. The soft ? start cap sets the initial
ramp rate using a typical 5.0 m A current. The typical value
to use for the soft ? start cap (SS), is typically set to 0.01 m F.
This results in a ramp time to 1.1 V of 2.2 ms based on
Equation 1.
Figure 25. 1.6 to 0.5 Dynamic VID Response
Css ^ iss
dtss
dvss
1.1 · V
2.2 · ms
+
dvss
dtss
and iss + 5 · m A
(eq. 1)
Css + 0.01 · m F
Figure 26. Dynamic VID Settling Time Rising
Figure 28. VR11 Startup
Figure 27. Dynamic VID Settling Time Falling
Figure 29. AMD Startup
http://onsemi.com
27
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