参数资料
型号: NCP5395MNR2G
厂商: ON Semiconductor
文件页数: 12/29页
文件大小: 0K
描述: IC PHASE CONTROLLER 2/3/4 48-QFN
标准包装: 2,500
应用: 控制器,Intel VR11.1
输入电压: 4.75 V ~ 5.25 V
输出数: 4
输出电压: 0.5 V ~ 1.6 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 带卷 (TR)
NCP5395
ELECTRICAL CHARACTERISTICS
0 ° C < T A < 70 ° C; 0 ° C < T J < 125 ° C; 4.75 < V CC < 5.25 V; All DAC Codes; C VCC = 0.1 m F unless otherwise noted.
Parameter
Test Conditions
Min
Typ
Max
Unit
VID7/VR11/AMD/LEGACY INPUT
Delay Before Latching VID Change (VID Deskewing)
AMD Upper Threshold
AMD Lower Threshold
Measured from the Edge of the 1st
VID Change
Note: When above this threshold
the controller will ramp directly to
VID without stopping at V boot
200
?
2.4
?
?
?
300
2.9
?
ns
V
V
ENABLE INPUT
Enable High Input Leakage Current
VR11.1 Threshold
AMD Upper Threshold
AMD Lower Threshold
AMD Total Hysteresis
Enable Delay Time
Pull ? up to 1.3 V
Rising ? Falling Threshold
Measure time from Enable
transitioning HI to when SS begins
?
450
?
0.9
?
?
?
600
1.3
1.1
200
3.5
200
770
1.5
?
?
?
nA
mV
V
V
mV
ms
CURRENT LIMIT
ILIM to VDRP Gain
ILIM to VRDP Gain in PSI 4 Phase
ILIM to VDRP Gain in PSI 3 Phase
ILIM to VDRP Gain in PSI 2 Phase
ILIM Pin Input Bias Current
ILIM Pin Working Voltage Range
0.99
?
?
?
?
0.1
1.00
0.25
0.333
0.5
0.1
?
1.01
?
?
?
1.0
2.0
V/V
V/V
V/V
V/V
m A
V
ILIM accuracy
Delay
Measured with respect to the ILIM
setting
? 10
?
?
?
10
120
mV
ns
OVERVOLTAGE PROTECTION
VR11 Over Voltage Threshold
AMD Over Voltage Threshold
Delay
DAC+
160
DAC+
210
?
DAC+
190
DAC+
235
?
DAC+
210
DAC+
260
100
mV
mV
ns
UNDERVOLTAGE PROTECTION
V CC UVLO Start Threshold
V CC UVLO Stop Threshold
V CC UVLO Hysteresis
4.0
3.8
?
4.25
4.05
200
4.5
4.3
?
V
V
mV
DAC OUTPUT
DAC Output Variation
DAC Output Variation
Output Source Current
Output Sink Current
I SOURCE = 200 m A, All VIDs
I SINK = 200 m A, All VIDs
V out = 1.6 V
V out = 0.3 V
? 3.0
? 3.0
0
5.0
0
0
?
?
3.0
3.0
5.0
16
%
%
mA
mA
Design guaranteed.
For propagation delays, “tpdh” refers to the specified signal going high “tpdl” refers to it going low. Reference Gate Timing Diagram.
Guaranteed by design; not tested in production.
Internal DAC voltage is centered 19 mV below the listed Voltage. For VR11.1/VR11.0/VR10
No DAC offset is implemented for AMD operation.
http://onsemi.com
12
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