参数资料
型号: NCP5395MNR2G
厂商: ON Semiconductor
文件页数: 8/29页
文件大小: 0K
描述: IC PHASE CONTROLLER 2/3/4 48-QFN
标准包装: 2,500
应用: 控制器,Intel VR11.1
输入电压: 4.75 V ~ 5.25 V
输出数: 4
输出电压: 0.5 V ~ 1.6 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 带卷 (TR)
NCP5395
ELECTRICAL CHARACTERISTICS
0 ° C < T A < 70 ° C; 0 ° C < T J < 125 ° C; 4.75 < V CC < 5.25 V; All DAC Codes; C VCC = 0.1 m F unless otherwise noted.
Parameter
Test Conditions
Min
Typ
Max
Unit
ERROR AMPLIFIER
Input Bias Current
? 200
?
200
nA
Open Loop DC Gain
Open Loop Unity Gain Bandwidth
Open Loop Phase Margin
Slew Rate
Maximum Output Voltage
Minimum Output Voltage
Output Source Current
Output Sink Current
C L = 60 pF to GND,
R L = 10 k W to GND
C L = 60 pF to GND,
R L = 10 k W to GND
C L = 60 pF to GND,
R L = 10 k W to GND
D V in = 100 mV, G = ? 10V/V,
D V out = 1.5 V ? 2.5 V,
C L = 60 pF to GND,
DC Load = ± 125 m A to GND
10 mV of Overdrive,
I SOURCE = 2.0 mA
10 mV of Overdrive,
I SINK = 500 m A
10 mV of Overdrive,
V out = 3.5 V
10 mV of Overdrive,
V out = 0.1 V
?
?
?
?
3.0
?
1.5
0.75
100
18
70
10
?
?
2.0
1.0
?
?
?
?
?
75
?
?
dB
MHz
°
V/ m s
V
mV
mA
mA
DIFFERENTIAL SUMMING AMPLIFIER
V+ Input Pull down Resistance
V+ Input Bias Voltage
Input Voltage Range (Note 4)
? 3 dB Bandwidth
Closed Loop DC gain VS to Diffout (Note 4)
Maximum Output Voltage
Minimum Output Voltage
Output Source Current
Output Sink Current
DRVON = low
DRVON = high
DRVON = low
DRVON = high
C L = 80 pF to GND,
R L = 10 k W to GND
VS+ to VS ? = 0.5 V to 1.6 V
10 mV of Overdrive,
I SOURCE = 2 mA
10 mV of Overdrive,
I SINK = 1 mA
10 mV of Overdrive,
V out = 3 V
10 mV of Overdrive,
V out = 0.2 V
?
?
?
?
? 0.3
?
0.98
3.0
?
1.5
1.0
0.6
6.0
0.5
0.86
?
15
1.0
?
?
2.0
1.5
?
?
?
?
3.0
?
1.02
?
0.5
?
?
k W
V
V
MHz
V/V
V
V
mA
mA
INTERNAL OFFSET VOLTAGE
Offset Voltage to the (+) Pin of the Error Amp & the
VDRP Pin
? 2
0
+2
mV
Design guaranteed.
For propagation delays, “tpdh” refers to the specified signal going high “tpdl” refers to it going low. Reference Gate Timing Diagram.
Guaranteed by design; not tested in production.
Internal DAC voltage is centered 19 mV below the listed Voltage. For VR11.1/VR11.0/VR10
No DAC offset is implemented for AMD operation.
http://onsemi.com
8
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