参数资料
型号: NCP5395MNR2G
厂商: ON Semiconductor
文件页数: 9/29页
文件大小: 0K
描述: IC PHASE CONTROLLER 2/3/4 48-QFN
标准包装: 2,500
应用: 控制器,Intel VR11.1
输入电压: 4.75 V ~ 5.25 V
输出数: 4
输出电压: 0.5 V ~ 1.6 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 带卷 (TR)
NCP5395
ELECTRICAL CHARACTERISTICS
0 ° C < T A < 70 ° C; 0 ° C < T J < 125 ° C; 4.75 < V CC < 5.25 V; All DAC Codes; C VCC = 0.1 m F unless otherwise noted.
Parameter
Test Conditions
Min
Typ
Max
Unit
VDROOP AMPLIFIER
Input Bias Current
Inverting Voltage Range
? 200
0
?
1.3
200
3.0
nA
V
Open Loop DC Gain
Open Loop Unity Gain Bandwidth
Open Loop Phase Margin
Slew Rate
Maximum Output Voltage
Minimum Output Voltage
Output Source Current
Output Sink Current
C L = 20 pF to GND including ESD
R L = 1 k W to GND
C L = 20 pF to GND including ESD
R L = 1 k W to GND
C L = 20 pF to GND including ESD
R L = 1 k W to GND
C L = 20 pF to GND including ESD
R L = 1 k W to GND
10 mV of Overdrive,
I SOURCE = 4.0 mA
10 mV of Overdrive,
I SINK = 1.0 mA
10 mV of Overdrive,
V out = 3.0 V
10 mV of Overdrive,
V out = 1.0 V
?
?
?
?
3.0
?
4.0
1.0
100
18
70
10
?
?
?
?
?
?
?
?
?
1.0
?
?
dB
MHz
°
V/ m s
V
V
mA
mA
CSSUM AMPLIFIER
Current Sense Input to CSSUM Gain
Current Sense Input to V DRP ? 3 dB Bandwidth
Current Summing Amp Output Offset Voltage
Maximum CSSUM Output Voltage
Minimum CSSUM Output Voltage
Output Source Current
Output Sink Current
? 75 mV < CS < 75 mV
C L = 10 pF to GND,
R L = 10 k W to GND
CSx ? CSNx = 0, CSx = 1 V
CSx ? CSxN = ? 0.2 V
(all phases) I SOURCE = 1 mA
CSx ? CSxN = 0.7 V
(all phases) I SINK = 1 mA
V out = 3.0 V
V out = 0.3 V
? 3.793
?
? 8.0
3.0
?
1.0
4.0
? 3.70
12
?
?
?
?
?
? 3.608
?
+8.0
?
0.3
?
?
V/V
MHz
mV
V
V
mA
mA
PSI
Enable High Input Leakage Current
Threshold
Delay
External 1k Pull ? up to 3.3 V
?
450
?
?
600
100
1.0
770
?
m A
mV
ns
DRVON
Output High Voltage
Output Low Voltage
Delay Time
Rise Time
Fall Time
Internal Pull ? Down Resistance
V CC Voltage when DRVON Output Valid
Sourcing 500 m A
Sinking 500 m A
Propagation delays
C L (PCB) = 20 pF,
D Vo = 10% to 90%
C L (PCB) = 20 pF,
D Vo = 10% to 90%
3.0
?
?
?
?
35
?
?
?
10
10
10
70
?
?
0.7
?
?
?
140
2.0
V
V
ns
ns
ns
k W
V
Design guaranteed.
For propagation delays, “tpdh” refers to the specified signal going high “tpdl” refers to it going low. Reference Gate Timing Diagram.
Guaranteed by design; not tested in production.
Internal DAC voltage is centered 19 mV below the listed Voltage. For VR11.1/VR11.0/VR10
No DAC offset is implemented for AMD operation.
http://onsemi.com
9
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