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参数资料
| 型号： | NCP5680MUTXG |
| 厂商： | ON Semiconductor |
| 文件页数： | 16/27页 |
| 文件大小： | 0K |
| 描述： | IC LED DRIVER WHT HI EFF 24-UQFN |
| 产品变化通告： | Product Obsolescence 30/Jun/2011 |
| 标准包装： | 3,000 |
| 拓扑： | 切换式电容器（充电泵） |
| 输出数： | 2 |
| 内部驱动器： | 无 |
| 类型 - 主要： | 闪灯/白光 |
| 类型 - 次要： | 白色 LED |
| 频率： | 850kHz ~ 1.15MHz |
| 电源电压： | 2.7 V ~ 5.5 V |
| 输出电压： | 4.5 V ~ 5.3 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-UFQFN 裸露焊盘 |
| 供应商设备封装： | 24-UQFN（3.5x3.5） |
| 包装： | 带卷 (TR) |
| 工作温度： | -40°C ~ 85°C |
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NCP5680
Load Connection
The primary function of the NCP5680 chip is to control
two high power LED arranged in the photo flash structure.
The LED are independently activated or de ? activated by
means of the I2C command.
In addition, the chip is capable to drive the Torch mode
or the Indicator function, the output LED current being
monitored by the associated current mirrors. Although it is
possible to connect several LED in parallel to share the
output current, such solution is discouraged since the
matching between the LED can no longer be guaranteed.
However, using a dual NMOS device in the same
package provides a way to drive up to four LEDs with full
flash current capability per LED, as depicted in Figure 11.
LED Programming Operation
All the electrical biases of each LED are set up by means
of an hexadecimal byte coming from the I2C port. The Iout
peak current, the flash pulse duration and the flash delays
are stored into registers associated to each LED.
Consequently, each LED can have a different amplitude,
duration and delay during a single photo flash sequence.
The mode of operation ? either Video torch or Flash, or
Picture Light or ICON ? is selected by the I2C command.
In addition, the photo flash sequence can be activated either
by the appropriate I2C command, or by means of the
dedicated TRGFL pin, assuming the chip has been
previously activated (the TRGFL signal has no effect if
NCP5680 is in shut down mode). The Time out is
automatically asserted when a pulsed flash is activated.
Power Flash
The I ? LED flash current is regulated by means of the
analog loop built with the external NMOS device
associated to the external shunt resistor: see Figure 10. The
internal operational amplifier uses the reference voltages,
as defined by the contain of register FILED1 and FILED2,
to monitor the current flowing in the loop. Basically, the
Voltage to current ratio is 100 mV/A: a 100 m W resistor will
force a 1 A I ? LED current with 100 mV programmed at the
FILED1 or FILED2 register. Of course, different value for
the shunt resistor can be implemented, but care must be
observed as it might be difficult to extract a low drop
voltage in a noisy environment.
The power flash sequence can be activated in two ways:
1. Using the I2C command associated to the
CONFIG1register: the positive going of the bit
I2CTRG signal fires the pulsed flash (the pulse
width depends upon the contain of FLWID1 &
FLWID2 registers), the delays are activated,
depending upon the contain of FLDY1 & FLDY2
registers, the time out is engaged, the output
current is forced to the values previously stored
into the FILED1 and FILED2 registers. The flash
can be as short as 100 m s, with 255 ms as a
maximum duration (see TOUT register). The
I2CTRG bit in the CONFIG1 register is
automatically reset to Low when the flash pulse
is completed.
2. Using a direct command through the TRGFL pin,
assuming the EXTRG bit in the CONFIG1
register is set to High. In this case, the time out is
activated but the timers and the pulse width
registers are de ? activated since the duration of
the pulsed flash depends solely upon the duration
of the signal present at the TRGFL pin.
T FW ≥ 10 m s
TRIGFL
FLASH
PHOTO SENSE
Mode
PHOTO SENSE
Feedback
Charge Pump
Active
Standby
Re ? cycle: 2sec @
Cout = 1F, Vbat = 4V
Photo sense function activated
Illumination level is preset by
the I2C previous message
T FW
Photo sense feedback
TRIGFL Pulse
Figure 11. Basic Operation Timings
http://onsemi.com
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