参数资料
型号: NCP6334BMTBBTBG
厂商: ON Semiconductor
文件页数: 13/14页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 2A 8-WDFN
标准包装: 3,000
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.6 V ~ 5.5 V
输入电压: 2.3 V ~ 5.5 V
PWM 型: 电压模式
频率 - 开关: 3MHz
电流 - 输出: 2A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-WFDFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 8-WDFN(2x2)
NCP6334B, NCP6334C
LAYOUT CONSIDERATIONS
Electrical Layout Considerations
Good electrical layout is a key to make sure proper
operation, high efficiency, and noise reduction. Electrical
layout guidelines are:
? Use wide and short traces for power paths (such as
PVIN, VOUT, SW, and PGND) to reduce parasitic
inductance and high ? frequency loop area. It is also
good for efficiency improvement.
? The device should be well decoupled by input capacitor
and input loop area should be as small as possible to
reduce parasitic inductance, input voltage spike, and
noise emission.
? SW node should be a large copper pour, but compact
because it is also a noise source.
? It would be good to have separated ground planes for
PGND and AGND and connect the two planes at one
point. Directly connect AGND pin to the exposed pad
and then connect to AGND ground plane through vias.
Try best to avoid overlap of input ground loop and
output ground loop to prevent noise impact on output
regulation.
GND
? Arrange a “quiet” path for output voltage sense and
feedback network, and make it surrounded by a ground
plane.
Thermal Layout Considerations
Good thermal layout helps high power dissipation from a
small package with reduced temperature rise. Thermal
layout guidelines are:
? The exposed pad must be well soldered on the board.
? A four or more layers PCB board with solid ground
planes is preferred for better heat dissipation.
? More free vias are welcome to be around IC and/or
underneath the exposed pad to connect the inner ground
layers to reduce thermal impedance.
? Use large area copper especially in top layer to help
thermal conduction and radiation.
? Do not put the inductor to be too close to the IC, thus
the heat sources are distributed.
VIN
P
P
P
P
P
P
PGND
SW
AGND
1
2
3
A
A
8
7
6
PVIN
AVIN
MODE/PG
F
FB
4
A
5
EN
L
P
P
O
P
P
P
P
P
P
P
F
Cfb
R1
O
R2
A
VOUT
GND
Figure 20. Recommended PCB Layout for Application Boards
http://onsemi.com
13
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