- 您现在的位置：买卖IC网 > PDF目录19223 > NCV7361ADG (ON Semiconductor)IC REG LDO 5V 50MA 8-SOIC PDF资料下载
参数资料
| 型号： | NCV7361ADG |
| 厂商： | ON Semiconductor |
| 文件页数： | 19/27页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 5V 50MA 8-SOIC |
| 产品变化通告： | Product Discontinuation 27/Jan/2012 |
| 标准包装： | 98 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 5V |
| 输入电压： | 5.25 V ~ 18 V |
| 稳压器数量： | 1 |
| 电流 - 输出： | 50mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页当前第19页第20页第21页第22页第23页第24页第25页第26页第27页
NCV7361A
MIN/MAX SLOPE TIME CALCULATION
V BUS
100%
95%
60%
BUS
40%
5%
0%
t sdom
V dom
Figure 27. Slope Time Calculation
t srec
The slew rate of the bus voltage is measured between
40% and 60% of the output voltage swing (linear region).
The output voltage swing is the difference between
dominant and recessive bus voltage.
dV dt + 0.2 * Vswing (t40% ? t60%)
The slope time is the extension of the slew rate tangent
until the upper and lower voltage swing limits:
tslope + 5 * (t40% ? t60%)
50
45
40
35
30
25
20
15
The slope time of the recessive to dominant edge is directly
determined by the slew rate control of the transmitter:
tslope + Vswing dV dt
The dominant to recessive edge is influenced from the
network time constant and the slew rate control, because
10
5
0
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
V SUP (V)
PDmax + J
* PD_TX_max @ VSUP
IVOUTmax + R q J ? A
it’s a passive edge. In case of low battery voltages and high
bus loads the rising edge is only determined by the network.
If the rising edge slew rate exceeds the value of the
dominant one, the slew rate control determines the rising
edge.
Power Dissipation and Operating Range
The max power dissipation depends on the thermal
resistance of the package and the PCB, the temperature
difference between Junction and Ambient as well as the
airflow.
The power dissipation can be calculated with:
PD + (VSUP * VOUT) * IVOUT ) PD_TX
The power dissipation of the transmitter P D_TX depends
on the transceiver configuration and its parameters as well
as on the bus voltage V BUS = V BAT ? V D , the resulting
termination resistance R L , the capacitive bus load C L and
the bit rate. Figure 28 shows the dependence of power
dissipation of the transmitter as function of V SUP . The
conditions for calculation the power dissipation was:
R L = 500 W , C L = 10 nF, Bitrate = 20 kbit and duty cycle
on TxD of 50%.
Figure 28. Power Dissipation LIN Transceiver
@ 20 kbit
The permitted package power dissipation can be
calculated:
T * TA
R q J ? A
If we consider that P D_TX_max = f(V SUP ), it can be
calculated the max output current IV OUT on V OUT :
TJ ? TA
VSUP * VOUT
T J ? T A is the temperature difference between junction
and ambient, and R th is the thermal resistance of the
package. The thermal energy is transferred via the package
and the pins to the ambient. This transfer can be improved
with additional ground areas on the PCB as well as ground
areas under the IC.
http://onsemi.com
19
相关PDF资料 |
PDF描述 |
|---|---|
| TAJE106K035RNJ | CAP TANT 10UF 35V 10% 2917 |
| VI-JTM-CW-S | CONVERTER MOD DC/DC 10V 100W |
| HWS50-48/HD | PWR SUP IND 48V 52.8W 1.1A |
| HCC44DRAS-S734 | CONN EDGECARD 88POS .100 R/A PCB |
| MUR460RLG | DIODE ULTR FAST 4A 600V DO-201AD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NCV7361ADR2 | 功能描述:低压差稳压器 - LDO LDO REG w/Integrated RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
| NCV7361ADR2G | 功能描述:低压差稳压器 - LDO ANA 10mA PLUS LIN RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
| NCV7380 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:LIN Transceiver |
| NCV7380/D | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LIN Transceiver |
| NCV7380_07 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:LIN Transceiver |
发布紧急采购，3分钟左右您将得到回复。