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参数资料
| 型号： | NCV7513AFTR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 16/23页 |
| 文件大小： | 0K |
| 描述： | IC PREDRIVER HEX LOW SIDE 32LQFP |
| 标准包装： | 2,000 |
| 系列： | FLEXMOS™ |
| 配置： | 低端 |
| 输入类型： | 非反相 |
| 延迟时间： | 1.0µs |
| 配置数： | 6 |
| 输出数： | 6 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 带卷 (TR) |
NCV7513A
V CC1
Status Flag (STAB)
The open ? drain active ? low status flag output can be used
?
A
B
?
CMP1
+
+
CMP2
V OL
V SG
V CTR
+
_
D3
D4
I SG
D1
D2
I OL
1600
DZ1
(V CL )
50
DRN X
R DX
+V OS
V LOAD
R LOAD
V X
R SG
to provide a host controller with information about the state
of a channel’s DRN x feedback. Feedback from all channels
is logically ORed to the flag (Figure 16). The STAB
outputs from several devices can be wire ? ORed to a
common pullup resistor connected to the controller ’s 3.3 or
5.0 V V DD supply.
When ENA1 is high, the drain feedback from a channel’s
DRN x input is compared to the V OL reference without
regard to ENA2 or the commanded state of the channel’s
driver. The flag is reset and disabled when ENA1 is low or
when all mask bits are set. See Table 9 for additional
K X
Q
+
DRN X
CLR
Figure 15. Short to GND/Open ? Load Detection
When a channel is off and V LOAD and R LOAD are
present, R SG is absent, and V DRNX >> V CTR , bias current
I OL is supplied from V LOAD to ground through external
resistors R LOAD and R DX , and through the internal 1650 W
resistance and bridge diode D2. Bias current I SG is supplied
from V CC1 to V CTR through D3. No fault is detected if the
feedback voltage (V LOAD minus the total voltage drop
caused by I SG and the resistance in the path) is greater than
V OL .
When either V LOAD or R LOAD and R SG are absent, the
bridge will self ? bias so that the voltage at DRN X will settle
to about V CTR . An open load fault can be detected since the
feedback is between V SG and V OL .
Short to GND detection can tolerate up to a 1.0 V offset
(V OS ) between the NCV7513A’s GND and the short. When
R SG is present and V DRNX << V CTR , bias current I SG is
supplied from V CC1 to V OS through D1, the internal
1650 W , and the external R DX and R SG resistances. Bias
current I OL is supplied from V CTR to ground through D4.
A “weak” short to GND can be detected when either
V LOAD or R LOAD is absent and the feedback (V OS plus the
total voltage rise caused by I OL and the resistance in the
path) is less than V OL .
When V LOAD and R LOAD are present, a voltage divider
between V LOAD and V OS is formed by R LOAD and R SG . A
“hard” short to GND may be detected in this case
details.
The flag is set (low) when the feedback voltage is less
than V OL , and the channel’s mask bit (Table 5) is cleared.
The flag is reset (hi ? Z) when the feedback voltage is
greater than V OL , and the channel’s mask bit is cleared.
OTHER
CHANNELS STAB
V OL ? D
CMP1
A
500 kHz
POR
ENA1
Figure 16. STAB Flag Logic
Fault Flag (FLTB)
The open ? drain active ? low fault flag output can be used
to provide immediate fault notification to a host controller.
Fault detection from all channels is logically ORed to the
flag (Figure 17). The FLTB outputs from several devices
can be wire ? ORed to a common pullup resistor connected
to the controller ’s 3.3 or 5.0 V V DD supply.
The flag is set (low) when a channel detects any fault, the
channel’s mask bit (Table 5) is cleared, and both ENA x and
CSB are high. The flag is reset (hi ? Z) and disabled when
either ENA1 or CSB is low. See Table 9 for additional
details.
depending on the ratio of R LOAD and R SG and the values of
R DX , V LOAD , and V OS .
Note that the comparators see a voltage drop or rise due
only to the 50 W internal resistance and the bias currents.
This produces a small difference in the comparison to the
actual feedback voltage at the DRN X input.
Several equations for choosing R DX and for predicting
open load or short to GND resistances, and a discussion of
ENA2
ENA1
CSB
K X
FAULT X
POR
OTHER
CHANNELS
S
Q
R
(RESET DOMINANT)
FLTB
the dynamic behavior of the short to GND/open load
diagnostic are provided in the Applications Information
section of this data sheet.
http://onsemi.com
16
Figure 17. FLTB Flag Logic
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