参数资料
型号: NE570DG
厂商: ON Semiconductor
文件页数: 9/10页
文件大小: 0K
描述: IC COMPANDOR DUAL GAIN 16-SOIC
标准包装: 47
类型: 压缩扩展器
应用: 蜂窝式无线电,播放器
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 管件
其它名称: NE570DG-ND
NE570DGOS
NE570
http://onsemi.com
8
this, which means our overall offsets are typically about mV.
The distortion is not affected by the magnitude of the gain
control current, and it does not increase as the gain is
changed. This second harmonic distortion could be
eliminated by making perfect transistors, but since that
would be difficult, we have had to resort to other methods.
A trim pin has been provided to allow trimming of the
internal offsets to zero, which effectively eliminated second
harmonic distortion. Figure 14 shows the simple trim
network required.
3.6 V
VCC
R
20 k
W
6.2 k
W
To THD Trim
≈200 pF
Figure 14. THD Trim Network
Figure 15 shows the noise performance of the
DG cell. The
maximum output level before clipping occurs in the gain cell
is plotted along with the output noise in a 20 kHz bandwidth.
Note that the noise drops as the gain is reduced for the first
20 dB of gain reduction. At high gains, the signal to noise
ratio is 90 dB, and the total dynamic range from maximum
signal to minimum noise is 110 dB.
VCA GAIN (dB)
+20
OUTPUT
(dBm)
0
20
40
60
80
100
40
20
0
MAXIMUM
SIGNAL LEVEL
NOISE IN
20 kHz BW
90 dB
110 dB
Figure 15. Dynamic Range
Control signal feedthrough is generated in the gain cell by
imperfect device matching and mismatches in the current
sources, I1 and I2. When no input signal is present, changing
IG will cause a small output signal. The distortion trim is
effective in nulling out any control signal feedthrough, but
in general, the null for minimum feedthrough will be
different than the null in distortion. The control signal
feedthrough can be trimmed independently of distortion by
tying a current source to the
DG input pin. This effectively
trims I1. Figure 16 shows such a trim network.
RSELECT FOR
3.6 V
470 k
W
TO PIN 3 OR 14
100 k
W
VCC
Figure 16. Control Signal Feedthrough
OPERATIONAL AMPLIFIER
The main op amp shown in the chip block diagram is
equivalent to a 741 with a 1.0 MHz bandwidth. Figure 17
shows the basic circuit. Split collectors are used in the input
pair to reduce gM, so that a small compensation capacitor of
just 10 pF may be used. The output stage, although capable
of output currents in excess of 20 mA, is biased for a low
quiescent current to conserve power. When driving heavy
loads, this leads to a small amount of crossover distortion.
OUT
Q5
I1
I2
Q1
D2
IN
+IN
Q2
Q3
Q4
CC
D1
Q6
Figure 17. Operational Amplifier
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