参数资料
型号: NL17SZ74USG
厂商: ON Semiconductor
文件页数: 1/6页
文件大小: 0K
描述: IC FLIP FLOP D-TYPE LOG US8
标准包装: 1
系列: 17SZ
功能: 设置(预设)和复位
类型: D 型
输出类型: 差分
元件数: 1
每个元件的位元数: 1
频率 - 时钟: 250MHz
延迟时间 - 传输: 2.2ns
触发器类型: 正边沿
输出电流高,低: 32mA,32mA
电源电压: 1.65 V ~ 5.5 V
工作温度: -55°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-VFSOP(0.091",2.30mm 宽)
包装: 标准包装
产品目录页面: 1126 (CN2011-ZH PDF)
其它名称: NL17SZ74USGOSDKR
Semiconductor Components Industries, LLC, 2013
May, 2013 Rev. 10
1
Publication Order Number:
NL17SZ74/D
NL17SZ74
Single D Flip Flop
The NL17SZ74 is a high performance, full function Edge triggered
D Flip Flop, with all the features of a standard logic device such as the
74LCX74.
Features
Extremely High Speed: tPD 2.6 ns (typical) at VCC = 5.0 V
Designed for 1.65 V to 5.5 V VCC Operation
5.0 V Tolerant Inputs Interface Capability with 5.0 V TTL Logic
LVTTL Compatible
LVCMOS Compatible
24 mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current (10 mA) Substantially Reduces
System Power Requirements
Replacement for NC7SZ74
Tiny Ultra Small Package Only 2.1 X 3.0 mm
High ESD Ratings: 4000 V Human Body Model
High ESD Ratings: 200 V Machine Model
Chip Complexity: FET = 64
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
These Devices are PbFree and are RoHS Compliant
TRUTH TABLE
Inputs
Outputs
Operating Mode
PR
CLR
CP
D
Q
L
H
L
H
L
X
H
L
H
L
H
Asynchronous Set
Asynchronous Clear
Undetermined
H
h
l
H
L
H
Load and Read Register
H
X
NC
Hold
H
= High Voltage Level
h
= High Voltage Level One Setup Time Prior to the LowtoHigh
Clock Transition
L
= Low Voltage Level
l
= Low Voltage Level One Setup Time Prior to the LowtoHigh
Clock Transition
NC
= No Change
X
= High or Low Voltage Level and Transitions are Acceptable
= LowtoHigh Transition
= Not a LowtoHigh Transition
For ICC reasons, DO NOT FLOAT Inputs
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
ORDERING INFORMATION
MARKING DIAGRAM
US8
US SUFFIX
CASE 493
PINOUT DIAGRAM
VCC
PR
CLR
Q
CP
D
Q
GND
1
2
3
4
8
7
6
5
Q
PR
7
5
D
2
CP
1
CLR
6
Q
3
VCC = 8, GND = 4
LOGIC DIAGRAM
MH M
G
MH
= Specific Device Code
M
= Date Code
G
= PbFree Package
(Note: Microdot may be in either location)
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