参数资料
型号: NLSF3T125MNR2G
厂商: ON Semiconductor
文件页数: 1/6页
文件大小: 0K
描述: IC BUS BUFFER TRI-ST QUAD 16QFN
标准包装: 1
逻辑类型: 缓冲器/线路驱动器,非反相
元件数: 4
每个元件的位元数: 1
输出电流高,低: 8mA,8mA
电源电压: 2 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-VFQFN 裸露焊盘
供应商设备封装: 16-QFN(3x3)
包装: 剪切带 (CT)
其它名称: NLSF3T125MNR2GOSCT
Semiconductor Components Industries, LLC, 2011
June, 2011 Rev. 5
1
Publication Order Number:
NLSF3T125/D
NLSF3T125
Quad Bus Buffer
with 3State Control Inputs
The NLSF3T125 is a high speed CMOS quad bus buffer fabricated
with silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS
low power dissipation.
The NLSF3T125 requires the 3state control input (OE) to be set
High to place the output into the high impedance state.
The T125 inputs are compatible with TTL levels. This device can be
used as a level converter for interfacing 3.3 V to 5.0 V, because it has
full 5.0 V CMOS level output swings.
The NLSF3T125 input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when VCC = 0 V. These
input and output structures help prevent device destruction caused by
supply voltage input/output voltage mismatch, battery backup, hot
insertion, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
High Speed: tPD = 3.8 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 4.0 mA (Max) at TA = 25°C
TTLCompatible Inputs: VIL = 0.8 V; VIH = 2.0 V
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: Human Body Model; > 2000 V,
Machine Model; > 200 V
Chip Complexity: 72 FETs or 18 Equivalent Gates
These Devices are PbFree and are RoHS Compliant
NLSF3T125
Inputs
Output
FUNCTION TABLE
Y
AOE
H
L
X
L
H
L
Z
MARKING DIAGRAM
QFN16
CASE 485G
http://onsemi.com
NLSF3T125 = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
NLSF3
T125
ALYWG
G
(Note: Microdot may be in either location)
1
ORDERING INFORMATION
Device
QFN16
(PbFree)
Shipping
3000/Tape & Reel
NLSF3T125MNR2G
Package
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
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