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| 型号： | NOII5FM1300A-QDC |
| 厂商： | ON Semiconductor |
| 文件页数： | 10/33页 |
| 文件大小： | 0K |
| 描述： | SENSOR IMAGE 1.3MP CMOS 84-LCC |
| 标准包装： | 1 |
| 象素大小： | 6.7µm x 6.7µm |
| 有源象素阵列： | 1280H x 1024V |
| 每秒帧数： | 27 |
| 电源电压： | 3 V ~ 4.5 V |
| 类型： | CMOS 成像 |
| 封装/外壳： | 84-LCC |
| 供应商设备封装： | 84-LCC（18x18） |
| 包装： | 托盘 |
| 请注意： | * |
| 其它名称： | CYII5FM1300AB-QDC CYII5FM1300AB-QDC-ND |
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NOII5SM1300A
Global Shutter Supply Considerations
The recommended supply voltage settings listed in
Table 8 are used when the sensor is in global shutter mode
only.
Table 9. DUAL SHUTTER RECOMMENDED SUPPLY
SETTINGS
Parameter Description Typ Units
VDDH Voltage on HOLD switches. +4.5 V
Table 8. GLOBAL SHUTTER RECOMMENDED
SUPPLY SETTINGS
Parameter Description Typ
VDDH Voltage on HOLD +4.5
switches.
VDDR_LEFT Highest reset voltage. +4.5
Units
V
V
VDDR_LEFT
VDDC
VDDA
VDDD
Highest reset voltage.
Pixel core voltage.
Analog supply voltage of
the image core.
Digital supply voltage of the
image core.
+4.5
+3.0
+3.3
+3.3
V
V
V
V
VDDC
Pixel core voltage.
+3.3
V
GNDA
Analog ground.
0
V
VDDA
VDDD
GNDA
GNDD
GND_AB
Analog supply voltage of
the image core.
Digital supply voltage of
the image core.
Analog ground.
Digital ground.
Anti-blooming ground.
+3.3
+3.3
0
0
0
V
V
V
V
V
GNDD Digital ground. 0 V
GND_AB Anti-blooming ground. 0 V
Image Core Biasing Signals
Table 10 summarizes the biasing signals required to drive
the IBIS5-1300. For optimization on speed and power
dissipation of all internal blocks, several biasing resistors are
needed.
Dual Shutter Supply Considerations
If you analyze the supply settings listed in Table 8, you can
see some fixed column non-uniformities (FPN) when
operating in rolling shutter mode. If a dual shutter mode
(both rolling and global shutter) is required during
operation, you must apply the supply settings listed in
Table 9 to achieve the best possible image quality.
Table 10. OVERVIEW OF BIAS SIGNALS
Each biasing signal determines the operation of a
corresponding module in the sense that it controls the speed
and power dissipation. The tolerance on the DC-level of the
bias levels can vary ± 150 mV due to process variations.
Signal
DEC_CMD
DAC_VHIGH
DAC_VLOW
AMP_CMD
COL_CMD
PC_CMD
ADC_CMD
ADC_VHIGH
ADC_VLOW
Comment
Connect to VDDA with R = 51 k W and decouple to GNDA with C = 100 nF.
Connect to VDDA with R = 0 W .
Connect to GNDA with R = 0 W .
Connect to VDDA with R = 51 k W and decouple to GNDA with C = 100 nF.
Connect to VDDA with R = 51 k W and decouple to GNDA with C = 100 nF.
Connect to VDDA with R = 22 k W and decouple to GNDA with C = 100 nF.
Connect to VDDA with R = 51 k W and decouple to GNDA with C = 100 nF.
Connect to VDDA with R = 230 W and decouple to GNDA with C = 100 nF.
Connect to GNDA with R = 410 W and decouple to GNDA with C = 100 nF.
Related module
Decoder stage.
High level of DAC.
Low level of DAC.
Output amplifier stage.
Columns amplifiers stage.
Pre-charge of column
busses.
Analog stage of ADC.
High level of ADC.
Low level of ADC.
DC-Level
1.0 V
3.3 V
0.0 V
1.2 V
1.0 V
1.17 V
1.0 V
2.7 V
1.2 V
http://onsemi.com
10
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