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| 型号： | NOII5FM1300A-QDC |
| 厂商： | ON Semiconductor |
| 文件页数： | 20/33页 |
| 文件大小： | 0K |
| 描述： | SENSOR IMAGE 1.3MP CMOS 84-LCC |
| 标准包装： | 1 |
| 象素大小： | 6.7µm x 6.7µm |
| 有源象素阵列： | 1280H x 1024V |
| 每秒帧数： | 27 |
| 电源电压： | 3 V ~ 4.5 V |
| 类型： | CMOS 成像 |
| 封装/外壳： | 84-LCC |
| 供应商设备封装： | 84-LCC（18x18） |
| 包装： | 托盘 |
| 请注意： | * |
| 其它名称： | CYII5FM1300AB-QDC CYII5FM1300AB-QDC-ND |
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NOII5SM1300A
P_WRITE loads the parallel data into the internal register of
the IBIS5-1300 where it is decoded (see Figure 19).
P_DATA (15:12) address bits REG_ADDR (3:0); P_DATA
(11:0) data bits REG_DATA (11:0).
Serial 3-Wire Interface
The serial 3-wire interface (or serial-to-parallel Interface)
uses a serial input to shift the data in the register buffer.
When the complete data word is shifted into the register
buffer the data word is loaded into the internal register where
it is decoded (see Figure 19). S_DATA (15:12) address bits
REG_ADDR (3:0); S_DATA (11:0) data bits REG_DATA
(11:0). When S_EN is asserted the parallel data is loaded
into the internal registers of the sensor. The maximum tested
frequency of S_DATA is 2.5 MHz.) The serial 2-wire
interface is not operational in the IBIS5-1300 image sensor.
Use the 3-wire SPI interface to load the sensor registers.
Figure 19. Parallel Interface Timing
TIMING DIAGRAMS
Frame Rate
The pixel rate for this sensor is high enough to support a
frame rate of greater than 100 Hz for a window size of
640 x 480 pixels (VGA format). Considering a row
blanking time of 3.5 m s (as baseline, see also Internal clock
granularities (bits 4, 5, 6 and 7) on page 17), this requires a
minimum pixel rate of nearly 40 MHz. The final bandwidth
of the column amplifiers, output stage, and others is
determined by external bias resistors. With a nominal pixel
rate of 40 MHz, a full frame rate of a little more than 27
frames per second is obtained.
The frame period of the IBIS5-1300 sensor depends on the
shutter type.
Rolling Shutter
=> Frame period = (Nr. Lines * (RBT + pixel period * Nr.
Region-of-Interest (ROI) Read Out
Windowing is easily achieved by uploading the starting
point of the X- and Y-shift registers in the sensor registers
using the various interfaces. This downloaded starting point
initiates the shift register in the X- and Y-direction triggered
by the Y_START (initiates the Y-shift register) and the
Y_CLK (initiates the X-shift register) pulse. The minimum
step size for the x-address is two (only even start addresses
are chosen) and one for the Y-address (every line is
addressable). The frame rate increases almost linearly when
fewer pixels are read out. Table 20 gives an overview of the
achievable frame rates (in rolling shutter mode) with various
ROI dimensions.
Table 20. FRAME RATE VS. RESOLUTION
Pixels))
with:
Nr. Lines Number of lines read out each frame (Y)
Nr. Pixels Number of pixels read out each line (X)
RBT Row blanking time = 3.5 m s (typical)
Pixel period 1/40 MHz = 25 ns
Example Read out time of the full resolution at nominal
Image
Resolution
(X x Y)
1280 x 1024
640 x 480
100 x 100
Frame Rate
[frames/s]
27
100
1657
Frame
Readout Time
[ms]
36
10
0.6
Comment
Full resolution.
ROI read out.
ROI read out.
speed (40 MHz pixel rate):
Frame period = (1024 * (3.5 m s + 25 ns * 1280)) = 36.4 ms
= 27.5 fps
Global shutter
Frame period = Tint + Tread out
= Tint + (Nr. Lines * (RBT + pixel period * Nr. Pixels))
with: Tint Integration (exposure) time
Nr. Lines Number of lines read out each frame (Y)
Nr. Pixels Number of pixels read out each line (X)
RBT Row blanking time = 3.5 m s (typical)
Pixel period 1/40 MHz = 25 ns
Example Read out time of the full resolution at nominal
speed (40 MHz pixel rate) with an integration time of 1 ms:
Frame period = 1 ms + (1024 * (3.5 m s + 25 ns * 1280))
= 37.4 ms = 26.8 fps
Timing Requirements
There are six control signals that operate the image sensor:
? SS_START
? SS_STOP
? Y_CLOCK
? Y_START
? X_LOAD
? SYS_CLOCK
The external system generates these control signals with
following time constraints to SYS_CLOCK (rising edge =
active edge):
T SETUP >7.5 ns
T HOLD > 7.5 ns
It is important that these signals are free of any glitches.
http://onsemi.com
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