参数资料
型号: NOIL1SC4000A-GDC
厂商: ON Semiconductor
文件页数: 17/30页
文件大小: 0K
描述: IC IMAGE SENSOR 4MP 127-PGA
标准包装: 1
系列: *
象素大小: 12µm x 12µm
有源象素阵列: 2048H x 2048V
每秒帧数: 15
电源电压: 2.5V, 3.3V
类型: CMOS 成像
封装/外壳: *
供应商设备封装: *
包装: *
其它名称: CYIL1SC4000AA-GDC
CYIL1SC4000AA-GDC-ND
NOIL1SM4000A
P ixel 1
Pixel 2 0 .: Pixel period : 20 nsec
s aturated
Output 1
dark
Sync_x
Clock_x:
25MHz
Figure 18. Output Signal Related to Clock_x Signal
In the figure, shown from bottom to top: Clock_x, Sync_x
and output. Output level before the first pixel is the level of
the last pixel on previous line.
As soon as Sync_x is high and one rising edge of Clock_x
occurs, the pixels are brought to the analog outputs. This is
again the simulation result of a comparable sensor to show
the principle.
Note the time difference between the clock edge and the
moment the data is seen at the output. Because it is difficult
to predict this time difference in advance, have the ADC
sampling clock flexible to set an optimal ‘add sampling’
point. The time differences can easily vary between 5 ns and
15 ns and must be tested on the real devices.
Reduced ROT Timing
The ROT is the time between the selection of lines that
you must wait to get the data stable at the column amplifiers.
It is a loss in time, which should be reduced as much as
possible.
Standard Timing (200 ns)
In this case, the control signals Norowsel and pre_col are
made active for about 20 ns from the moment the next line
is selected. The time these pulses must be active is related to
the biasing resistance Pre_load. The lower this resistance,
the shorter the pulse duration of Norowsel and pre_col may
be. After these pulses are given, wait for at least 180 ns
before the first pixel is sampled. For this mode, Sh_col must
always be active (low).
Figure 19. Standard Timing for ROT (only pre_col and No_row_sel control signals are required)
In this case, the control signals Norowsel and pre_col are
made active for about 20 ns from the moment the next line
is selected. The time these pulses must be active is related to
the biasing resistance Pre_load. The lower this resistance,
the shorter the pulse duration of Norowsel and pre_col may
be. After these pulses are given, wait for at least 180 ns
before the first pixel is sampled. For this mode Sh_col must
be made active (low) all the time.
http://onsemi.com
17
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NOIL1SM1300AWES 制造商:ON Semiconductor 功能描述:PW/H