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参数资料
| 型号： | NP70N10KUF-E1-AY |
| 厂商： | Renesas Electronics America |
| 文件页数： | 4/11页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH 100V 70A TO-263 |
| 标准包装： | 800 |
| FET 型： | MOSFET N 通道，金属氧化物 |
| FET 特点： | 标准 |
| 漏极至源极电压(Vdss)： | 100V |
| 电流 - 连续漏极(Id) @ 25° C： | 70A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 20 毫欧 @ 35A，10V |
| Id 时的 Vgs(th)（最大）： | 3.3V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 75nC @ 10V |
| 输入电容 (Ciss) @ Vds： | 3750pF @ 25V |
| 功率 - 最大： | 1.8W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | TO-263-3，D²Pak（2 引线+接片），TO-263AB |
| 供应商设备封装： | TO-263 |
| 包装： | 带卷 (TR) |
NP70N10KUF
ELECTRICAL CHARACTERISTICS (T A = 25 ° C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate Leakage Current
BV DSS
I DSS
I GSS
I D = 250 μ A, V GS = 0 V
V DS = 100 V, V GS = 0 V
V GS = ± 20 V, V DS = 0 V
100
10
± 100
V
μ A
nA
Gate to Source Threshold Voltage
V GS(th)
V DS = V GS , I D = 250 μ A
1.7
2.5
3.3
V
Forward Transfer Admittance
Note
| y fs |
V DS = 10 V, I D = 20 A
11
22
S
Drain to Source On-state Resistance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Note
R DS(on)
C iss
C oss
C rss
t d(on)
t r
t d(off)
t f
Q G
Q GS
Q GD
V GS = 10 V, I D = 35 A
V DS = 25 V
V GS = 0 V
f = 1 MHz
V DD = 50 V, I D = 35 A
V GS = 10 V
R G = 0 Ω
V DD = 80 V
V GS = 10 V
I D = 70 A
17
2500
270
110
25
9
48
7
50
16
19
20
3750
410
200
53
23
96
18
75
m Ω
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
Body Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Note
V F(S-D)
t rr
Q rr
I F = 70 A, V GS = 0 V
I F = 70 A, V GS = 0 V
di/dt = 100 A/ μ s
1.0
88
245
1.5
V
ns
nC
Note Pulsed
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
PG.
D.U.T.
R G = 25 Ω
50 Ω
L
V DD
PG.
D.U.T.
R G
R L
V DD
V GS
Wave Form
V GS
0
10%
V GS
90%
V GS = 20 → 0 V
V DS
90%
90%
V DD
I D
I AS
BV DSS
V DS
V GS
0
τ
V DS
Wave Form
V DS
0
t d(on)
10%
t r
10%
t d(off)
t f
Starting T ch
τ = 1 μ s
Duty Cycle ≤ 1%
t on
t off
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
I G = 2 mA
R L
2
PG.
50 Ω
V DD
Data Sheet D18040EJ2V0DS
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