参数资料
| 型号： | NSD-1202-ASST |
| 厂商： | ams |
| 文件页数： | 10/14页 |
| 文件大小： | 0K |
| 描述： | IC DRIVER MOTOR SQUIGGLE 16-QFN |
| 产品培训模块： | Miniature Motion Control Overview |
| 标准包装： | 1 |
| 系列： | SQUIGGLE® |
| 应用： | 压电电机驱动器 |
| 评估套件： | 可供 |
| 输出数： | 2 |
| 电流 - 输出： | 25mA |
| 电压 - 负载： | 24 V ~ 40 V |
| 电源电压： | 2.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VQFN 裸露焊盘 |
| 供应商设备封装： | 16-QFN（4x4） |
| 包装： | 标准包装 |
| 其它名称： | NSD-1202-ASSTDKR |
NSD-1202
Data Sheet - D e t a i l e d D e s c r i p t i o n
7.8 Duty Cycle Register
A register is used to define the duty cycle (or pulse width) of the driver output signal for each motor. The register value is directly transferred to
the analog part.
Since changing the duty cycle will change the speed of the motor, this register can be used to control the speed of two motors independently.
(Motor speed can also be controlled by varying the voltage; however, one setting applies to both motors. See the previous section, Output
Voltage Register.)
To provide motor independent speed control, the duty cycle may be adjusted from 50% (max speed) down to ~12% (minimum speed). A lower
duty cycle could be used, but may not provide enough vibration amplitude to overcome the load.
The default value for this register set during power up or power down (XPD = LOW) is equal to 00h. In this case the default duty cycle of 50% is
generated. The resulting duty cycle and resolution of single steps is depending on the master clock frequency and the switching frequency of the
driver output.
In the following table an example for 20MHz clock input and 150kHz driver frequency is given. The value of the duty cycle register should not
exceed 50% of the period counter value.
Duty Cycle Register
0000 0000
0000 0001
0000 1101
0001 1011
0010 1000
0011 0101
0100 0010
0100 0011
www.austriamicrosystems.com/NSD-1202
Min
Revision 0.2
Typ
49.6/50.4
0.8
9.8
20.3
30.1
39.8
49.6
50.4
Max
Unit
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