参数资料
| 型号： | NSD-1202-ASST |
| 厂商： | ams |
| 文件页数： | 8/14页 |
| 文件大小： | 0K |
| 描述： | IC DRIVER MOTOR SQUIGGLE 16-QFN |
| 产品培训模块： | Miniature Motion Control Overview |
| 标准包装： | 1 |
| 系列： | SQUIGGLE® |
| 应用： | 压电电机驱动器 |
| 评估套件： | 可供 |
| 输出数： | 2 |
| 电流 - 输出： | 25mA |
| 电压 - 负载： | 24 V ~ 40 V |
| 电源电压： | 2.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VQFN 裸露焊盘 |
| 供应商设备封装： | 16-QFN（4x4） |
| 包装： | 标准包装 |
| 其它名称： | NSD-1202-ASSTDKR |
NSD-1202
Data Sheet - D e t a i l e d D e s c r i p t i o n
7.3 Register Map
The table below shows the registers which can be addressed over the I2C interface.
Description
Address
MSB
Data Byte
LSB
Period count A
Pulse count A (high byte)
1
00h
01h
X
h
X
d
X
X
X
X
X
X
X
X
X
Pulse count A (low byte)
Period count B
1
Pulse count B (high byte)
Pulse count B (low byte)
Output voltage
Duty cycle A
Duty cycle B
Reserved register
02h
03h
04h
05h
06h
07h
08h
10h
X
X
h
X
X
X
X
X
X
d
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1. The master clock doubling bit (‘h’) of both registers 01h and 04h must set in order for the doubling to take affect (even if only driving one
motor). Do not use clock doubling if the master clock has a frequency > 10 MHz.
7.4 Output Drivers
The output drivers operate rail to rail and are capable of driving a large capacitive load. In power-down mode the output drivers are pulled to
ground. The same applies when the motor is off.
Symbol
C LOAD
Parameter
Rise/fall time
Load capacitance
Switching frequency
Switching frequency step
Switching frequency duty cycle
Duty cycle accuracy
Phase shift
Phase shift error
Master clock frequency (CLK)
Conditions
C LOAD 600pF
The load capacitance may be lower
than 500pF but the lower the value
the shorter the rise time.
The accuracy of switching frequency
and phase shift will be defined
depending on master clock
frequency; the given values are for
20MHz master clock. Lower master
clock frequencies give higher
deviations. For Squiggle applications
20MHz clock is required, 10 MHz can
be used with the clock doubling
feature.
Clock doubling feature may be
employed when using a 10MHz or
less master clock frequency
Min
25
500
140
0.98
1
-1
1
Typ
100
600
170
1.45
±90
20
Max
250
700
180
1.61
50
+1
±3
20
Units
ns
pF
kHz
kHz
%
%
deg
deg
MHz
www.austriamicrosystems.com/NSD-1202
Revision 0.2
7 - 13
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