参数资料
| 型号： | NSD-2101-ASST |
| 厂商： | ams |
| 文件页数： | 7/23页 |
| 文件大小： | 0K |
| 描述： | IC DRIVER MOTOR SQUIGGLE 16-QFN |
| 产品培训模块： | Miniature Motion Control Overview |
| 标准包装： | 1 |
| 系列： | SQUIGGLE® |
| 应用： | 压电电机驱动器 |
| 评估套件： | 可供 |
| 输出数： | 1 |
| 电源电压： | 2.3 V ~ 5.5 V |
| 工作温度： | -30°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VQFN 裸露焊盘 |
| 供应商设备封装： | 16-QFN（4x4） |
| 包装： | 标准包装 |
| 其它名称： | NSD-2101-ASSTDKR |
NSD-2101
Datasheet - D e t a i l e d D e s c r i p t i o n
7 Detailed Description
?? Supply input
?? LDO and bypass capacitors
?? I2C interface
?? Registers
?? Oscillator
?? Frequency tracking
?? Full bridge driver
The input voltage is supplied directly to the full bridge driver. With a full bridge drive, each piezo element sees twice the input voltage (2 x VDD).
However, the average input voltage to the piezo can be regulated by the ASIC between VDD and 2 x VDD. This average voltage, which can be
set via I2C along with the duty cycle (or pulse width) of the drive signal, determines the speed of the motor. The result being at lower speeds, the
motor consumes less power.
I2C registers also define the initial switching frequency of the motor, which can be adjusted from 50 kHz to 200 kHz based on the type of motor
being driven. Other registers control motor direction and the number of pulses the motor is active (correlating to distance traveled). The XPD
input enables a stand-by mode.
7.1 Output Drivers
The output drivers operate rail to rail and are capable of driving capacitive load up to 60nF. The concept is based on two full bridges per motor.
The reduced voltage Squiggle motor consists of 2 plates per phase and 2 phases. In power down mode the output drivers are pulled to ground.
The same applies when the motor is off.
Table 6. Characteristics for Output Drivers
VDD=2.3V
VCO clock cycles
Symbol
f tr
f tf
C LOAD
I lim
f DFR
f DC
t DT
f PS
Parameter
Rise/fall time from 0.23V to 2.07V and
vice versa
Load capacitance
2
Current limit for driver outputs
3
Drive frequency range
Switching frequency duty cycle
Dead time (additional)
Phase shift
Conditions
C LOAD 50nF,
1
4
Min
0.08
10
1000
50
1
2
-160
Typ
4
Max
0.8
60
1600
200
50
9
+90
Units
μs
nF
mA
kHz
%
deg
f PSE
Phase shift error
±3
deg
1. Measured at 10% to 90% of minimum VDD=2.3V. Maximum with 4 clocks dead-time.
2. Current limit is valid for full bridge and half bridge configuration. Due to the dynamic behavior of the output driver the maximum current
limit can not be reached under all conditions. Device can only be used for direct motor drive.
3. For this frequency range, frequency tracking is implemented.
4. Error of dead time is maximum +1 VCO clock cycle.
Revision 0.6
6 - 22
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相关代理商/技术参数 |
参数描述 |
|---|---|
| NSD2101-DQFS | 制造商:AMSCO 制造商全称:austriamicrosystems AG 功能描述:Piezo Motor Driver ASIC for SQL-RV Series Reduced Voltage SQUIGGLE RV and UTAF Motors |
| NSD2101-DWLS | 制造商:AMSCO 制造商全称:austriamicrosystems AG 功能描述:Piezo Motor Driver ASIC for SQL-RV Series Reduced Voltage SQUIGGLE RV and UTAF Motors |
| NSD225 | 制造商:Microsemi Corporation 功能描述:BAE PN 3274989-7,REVJ - Bulk |
| NSD226M10 | 制造商:NEC 功能描述:SMT226D10V NEC brand bulk 100/bag VT77 |
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