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参数资料
| 型号： | NTE849 |
| 厂商： | NTE Electronics, Inc. |
| 英文描述： | Integrated Circuit TV Horizontal/Vertical Countdown Digital Sync System |
| 中文描述： | 集成电路电视水平/垂直倒计时数字同步系统 |
| 文件页数： | 1/5页 |
| 文件大小： | 33K |
| 代理商： | NTE849 |
NTE849
Integrated Circuit
TV Horizontal/Vertical Countdown
Digital Sync System
Description:
The NTE849 is an integrated circuit in a 14–Lead DIP type package designed for use in TV horizontal/
vetical countdown digital sync systems. In some video playback units, there are incorrect frequency
relationships between horizontal and field frequencies. Automatic forced asynchronous mode elimi-
nates jitter when equalizer pulses are correct, but these incorrect frequency relationships exist.
Automatic standard mode occurs upon detection of nine or more equalizing pulses during a six–line–
width vertical driving period after seven fields of coincidence between integrated vertical (IV) sync and
internal counter output. Standard mode is retained for seven fields of missing or mutilated vertical
sync pulses.
If two or more noise pulses are detected at Pin12 during a 384–line active scan time, a noise detector
reverts the system to standard mode at the next field of coincidence (without seven fields of coinci-
dene delay). Thus, the unit stays in standard mode during tuner channel changes.
An automatic mode–recognition system places the unit in standard mode for NTSC signals or into
non–synchronous mode for non–standard sync signals.
An external oscillator (NTE701) supplies an input to Pin9 that is 32 times the horizontal rate. An inter-
nal divide–by–16 counter converts this input (32f
H
) to 2f
H
for use elsewhere. This 32f
H
signal is further
divided to f
H
, which is available at Pin11 to drive the horizontal deflection circuits. A divide–by–525
counter further divides the 2f
H
signal to generate the vertical ramp generator timing pulses and the
vertical blanking pulse.
A phasing circuit (part of the mode recognition and vertical regeneration circuits) insures that the 525
counter is reset in coincidence with the vertical sync. It does this by comparing the internally gener-
ated vertical pulse with an extrnal integrated vertical sync signal applied to Pin12. The automatic
mode recognition circuit forces the NTE849 into the standard mode for NTSC signals or into the non–
synchronous mode for non–standard sync signals such as video games. An input control signal (or
no connection) at Pin8 places the NTE849 into non–synchronous operation.
A phasing and timing logic circuit checks to see if the line counter is in sync with the IV signal at Pin12.
Seven consecutive fields of in–phase coincidence with the IV signal are needed to achieve standard
mode in unless two or more noise pulses are de–detected at input Pin12 during the active scan time.
In this case, normal mode will be acquired in one field.
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