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参数资料
| 型号： | NTE849 |
| 厂商： | NTE Electronics, Inc. |
| 英文描述： | Integrated Circuit TV Horizontal/Vertical Countdown Digital Sync System |
| 中文描述： | 集成电路电视水平/垂直倒计时数字同步系统 |
| 文件页数： | 5/5页 |
| 文件大小： | 33K |
| 代理商： | NTE849 |
Notes (Cont
’
d):
Note14. Frequency at Pin9 (clock) divided by frequency at Pin3 (ramp control).
Note15. Initilize or repeat initilization procedure before doing this test.
Note16. Apply a pulse 1 clock wide, 7808 clocks after first positive transition at Pin3.
Note17. Default count determined by 684 x 16(H) = 10944.
Note18. Sync serrations = 9.
Note19. Hold
–
off count determined by 492 x 16(H) = 7872.
Note20. Number of clocks occurring within ramp gate period.
Note21. Number of clocks occurring during the blanking gate period.
Note22. This series of tests checks the mode recognition circuits. The first test after initialization ap-
plies 9 serrations at the sync input pin. The IC should go to the synchronous count ratio of
8400. During the next seven fields only 8 serrations are applied. The NTE849 should main-
tain the synchronous count ratio of 8400 for the first six fields. At the seventh field the
NTE849 should go to default count of 10944. The test concludes with a 9
–
serration input.
The NTE849 should revert to a synchronous count of 8400.
Note23. This test checks the operation of the out
–
of
–
sync detector by applying out
–
of
–
phase sync
pulses to Pin12. The NTE849 will count eight fields before resetting to the sync pulse.
Note24. Initialize by 8364 sync for eight fields before test.
Note25. This test verifies the operation of the fast resync performance by simulating a noise pulse
(5 to 50 clocks wide) applied to the IV pin 4000 to 6000 clocks (8ms to 12ms) after IV sync.
Initialize to non
–
sync mode before performing this test. The IC should resync in the next field
and be maintained for the standard confidence count of seven fields.
Pin Connection Diagram
V
CC
GND
Comp Sync Input
Vertical Sync Input
1
2
3
4
Vertical Height
Ramp Charge Cap
External Bias Load
5
Yoke Feedback
6
Vertical Driver
7
Vertical Blank Output
14
13
12
11
To Horizontal Deflection Circuit
10
Async Time Constant
9
32 x Horizontal
8
Mode Select
.600 (15.24)
1
7
14
8
.300
(7.62)
.200 (5.08)
Max
.100 (2.45)
.099 (2.5) Min
.785 (19.95)
Max
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