- 您现在的位置：买卖IC网 > PDF目录189414 > OR2T10A-4S256 (Electronic Theatre Controls, Inc.) Field-Programmable Gate Arrays PDF资料下载
参数资料
| 型号： | OR2T10A-4S256 |
| 厂商： | Electronic Theatre Controls, Inc. |
| 元件分类： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 现场可编程门阵列 |
| 文件页数： | 115/192页 |
| 文件大小： | 3148K |
| 代理商： | OR2T10A-4S256 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页当前第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页第190页第191页第192页
Lucent Technologies Inc.
29
Data Sheet
June 1999
ORCA Series 2 FPGAs
Programmable Input/Output Cells
(continued)
PIC Architectural Description
The PIC architecture given in Figure 26 is described
using the following letter references. The figure depicts
a PIC at the top of the array, so inter-PIC routing is hor-
izontal and the indirect PIC-PLC routing is horizontal to
vertical. In some cases, letters are provided in more
than one location to indicate the path of a line.
A. As in the PLCs, the PIC contains a set of lines which
run the length (width) of the array. The PXL lines
connect in the corners of the array to other PXL
lines. The PXL lines also connect to the PIC BIDI,
PIC BIDIH, and LLDRV lines. As in the PLC XL lines,
the PXH lines twist as they propagate through the
PICs.
B. As in the PLCs, the PIC contains a set of lines which
run one-half the length (width) of the array. The PXH
lines connect in the corners and in the middle of the
array perimeter to other PXH lines. The PXH lines
also connect to the PIC BIDI, PIC BIDIH, and
LLDRV lines. As in the PLC XH lines, the PXH lines
do not twist as they propagate through the PICs.
C. The PX2[3:0] lines span a length of two PICs before
intersecting with a CIP. The CIP allows the length of
a path using PX2 lines to be extended two PICs.
D. The PX1[3:0] lines span a single PIC before inter-
secting with a CIP. The CIP allows the length of a
path using PX1 lines to be extended by one PIC.
E. These are four dedicated direct output lines con-
nected to the output buffers. The DOUT[3:0] signals
go directly from a PLC latch/FF to an output buffer,
minimizing the latch/FF to pad propagation delay.
F. This is a direct path from the input pad to the PLC
latch/flip-flops in the two rows (columns) adjacent to
PICs. This input allows a reduced setup time. Direct
inputs from the top and bottom PIC rows are
PDINTB[3:0]. Direct inputs from the left and right
PIC columns are PDINLR[3:0].
G. The OUT[3:0], TS[3:0], and IN[3:0] signals for each
I/O pad can be routed directly to the adjacent PLC’s
switching lines.
H. The four TRIDI buffers allow connections from the
pads to the PLC XL lines. The TRIDIs also allow
connections between the PLC XL lines and the
PBIDI lines, which are described in J below.
I. The four TRIDIH buffers allow connections from the
pads to the PLC XH lines. The TRIDIHs also allow
connections between the PLC XH lines and the
pBIDIH lines, which are described in K below.
J. The PBIDI lines (bidi[3:0]) connect the PXL lines,
PXH lines, and the PX1 lines. These are bidirec-
tional in that the path can be from the PXL, PXH, or
PX1 lines to the XL lines, or from the XL lines to the
PXL, PXH, or PX1 lines.
K. The pBIDIH lines (BIDIH[3:0]) connect the PXL
lines, PXH lines, and the PX1 lines. These are bidi-
rectional in that the path can be from the PXL, PXH,
or PX1 lines to the XH lines, or from the XH lines to
the PXL, PXH, or PX1 lines.
L. The LLIN[3:0] lines provide a fast connection from
the I/O pads to the XL and XH lines.
M.This set of CIPs allows the eight X1 lines (four on
each side) of the PLC perpendicular to the PIC to be
connected to either the PX1 or PX2 lines in the PIC.
N. This set of CIPs allows the eight X4 lines (four on
each side) of the PLC perpendicular to the PIC to be
connected to the PX1 lines. This allows fast access
to/from the I/O pads from/to the PLCs.
O. All four of the PLC X4 lines in a group connect to all
four of the PLC X4 lines in the adjacent PLC through
a CIP. (This differs from the
ORCA 1C Series in
which two of the X4 lines in adjacent PLCs are
directly connected without any CIPs.)
P. The long-line driver (LLDRV) line can be driven by
the XSW4 switching line of the adjacent PLC. To pro-
vide connectivity to the pads, the LLDRV line can
also connect to any of the four PXH or to one of the
PXL lines. The 3-state enable (TS[i]) for all four I/O
pads can be driven by XSW4, PXH, or PXL lines.
Q. For fast clock routing, one of the four I/O pads in
each PIC can be selected to be driven onto a dedi-
cated clock line. The clock line spans the length
(width) of the PLC array. This dedicated clock line is
typically used as a clock spine. In the PLCs, the
spine is connected to an XL line to provide a clock
branch in the perpendicular direction. Since there is
another clock line in the PIC on the opposite side of
the array, only one of the I/O pads in a given row
(column) can be used to generate a global signal in
this manner, if all PLCs are driven by the signal.
相关PDF资料 |
PDF描述 |
|---|---|
| OR2T10A-4S240I | Field-Programmable Gate Arrays |
| OR2T10A-4S240 | Field-Programmable Gate Arrays |
| OR2T10A-4S208I | Field-Programmable Gate Arrays |
| OR2T10A-4S208 | Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 47pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-5%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1206; Termination: Solder Coated SnPb; Body Dimensions: 0.125" x 0.062" x 0.051"; Container: Bag; Features: MIL-PRF-55681: R Failure Rate |
| OR2T10A-4S160I | Field-Programmable Gate Arrays |
相关代理商/技术参数 |
参数描述 |
|---|---|
| OR2T10A5BA256-DB | 功能描述:FPGA - 现场可编程门阵列 1024 LUT 244 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR2T10A5J160-DB | 功能描述:FPGA - 现场可编程门阵列 1024 LUT 244 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR2T10A5S208-DB | 功能描述:FPGA - 现场可编程门阵列 1024 LUT 244 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR2T10A5S240-DB | 功能描述:FPGA - 现场可编程门阵列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR2T12A4BA256-DB | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Lattice Semiconductor Corporation 功能描述: |
发布紧急采购，3分钟左右您将得到回复。