- 您现在的位置：买卖IC网 > PDF目录189437 > OR2T26A-6S352 (Electronic Theatre Controls, Inc.) Field-Programmable Gate Arrays PDF资料下载
参数资料
| 型号： | OR2T26A-6S352 |
| 厂商： | Electronic Theatre Controls, Inc. |
| 元件分类： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 现场可编程门阵列 |
| 文件页数： | 130/192页 |
| 文件大小： | 3148K |
| 代理商： | OR2T26A-6S352 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页当前第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页第190页第191页第192页
42
Lucent Technologies Inc.
Data Sheet
ORCA Series 2 FPGAs
June 1999
FPGA States of Operation (continued)
Start-Up
After configuration, the FPGA enters the start-up
phase. This phase is the transition between the config-
uration and operational states and begins when the
number of CCLKs received after INIT goes high is equal
to the value of the length count field in the configuration
frame and when the end of configuration frame has
been written. The system design issue in the start-up
phase is to ensure the user I/Os become active without
inadvertently activating devices in the system or caus-
ing bus contention. A second system design concern is
the timing of the release of global set/reset of the PLC
latches/FFs.
There are configuration options that control the relative
timing of three events: DONE going high, release of the
set/reset of internal FFs, and user I/Os becoming
active. Figure 38 shows the start-up timing for both the
ORCA and ATT3000 Series FPGAs. The system
designer determines the relative timing of the I/Os
becoming active, DONE going high, and the release of
the set/reset of internal FFs. In the
ORCA Series
FPGA, the three events can occur in any arbitrary
sequence. This means that they can occur before or
after each other, or they can occur simultaneously.
There are four main start-up modes: CCLK_NOSYNC,
CCLK_SYNC, UCLK_NOSYNC, and UCLK_SYNC.
The only difference between the modes starting with
CCLK and those starting with UCLK is that for the
UCLK modes, a user clock must be supplied to the
start-up logic. The timing of start-up events is then
based upon this user clock, rather than CCLK. The dif-
ference between the SYNC and NOSYNC modes is
that, for SYNC mode, the timing of two of the start-up
events (release of the set/reset of internal FFs and the
I/Os becoming active) is triggered by the rise of the
external DONE pin followed by a variable number of ris-
ing clock edges (either CCLK or UCLK). For the
NOSYNC mode, the timing of these two events is
based only on either CCLK or UCLK.
DONE is an open-drain bidirectional pin that may
include an optional (enabled by default) pull-up resistor
to accommodate wired ANDing. The open-drain DONE
signals from multiple FPGAs can be tied together
(ANDed) with a pull-up (internal or external) and used
as an active-high ready signal, an active-low PROM
enable, or a reset to other portions of the system.
When used in SYNC mode, these ANDed DONE pins
can be used to synchronize the other two start-up
events, since they can all be synchronized to the same
external signal. This signal will not rise until all FPGAs
release their DONE pins, allowing the signal to be
pulled high.
The default for
ORCA is the CCLK_SYNC synchro-
nized start-up mode where DONE is released on the
first CCLK rising edge, C1 (see Figure 38). Since this is
a synchronized start-up mode, the open-drain DONE
signal can be held low externally to stop the occurrence
of the other two start-up events. Once the DONE pin
has been released and pulled up to a high level, the
other two start-up events can be programmed individu-
ally to either happen immediately or after up to four ris-
ing edges of CCLK (Di, Di + 1, Di + 2, Di + 3, Di + 4).
The default is for both events to happen immediately
after DONE is released and pulled high.
A commonly used design technique is to release
DONE one or more clock cycles before allowing the I/O
to become active. This allows other configuration
devices, such as PROMs, to be disconnected using the
DONE signal so that there is no bus contention when
the I/Os become active. In addition to controlling the
FPGA during start-up, other start-up techniques that
avoid contention include using isolation devices
between the FPGA and other circuits in the system,
reassigning I/O locations and maintaining I/Os as
3-stated outputs until contentions are resolved.
Each of these start-up options can be selected during
bit stream generation in
ORCA Foundry, using
Advanced Options. For more information, please see
the
ORCA Foundry documentation.
Reconfiguration
To reconfigure the FPGA when the device is operating
in the system, a low pulse is input into PRGM. The con-
figuration data in the FPGA is cleared, and the I/Os not
used for configuration are 3-stated. The FPGA then
samples the mode select inputs and begins reconfigu-
ration. When reconfiguration is complete, DONE is
released, allowing it to be pulled high.
相关PDF资料 |
PDF描述 |
|---|---|
| OR2T26A-6S352I | Field-Programmable Gate Arrays |
| OR2T26A-6S432 | Field-Programmable Gate Arrays |
| OR2T26A-6S432I | Field-Programmable Gate Arrays |
| OR2T26A-6T208 | Field-Programmable Gate Arrays |
| OR2T26A-6T208I | Field-Programmable Gate Arrays |
相关代理商/技术参数 |
参数描述 |
|---|---|
| OR2T26A7BA352-DB | 功能描述:FPGA - 现场可编程门阵列 2304 LUT 326 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR2T26A7BC432-DB | 功能描述:FPGA - 现场可编程门阵列 2304 LUT 326 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR2T26A7PS208-DB | 功能描述:FPGA - 现场可编程门阵列 2304 LUT 326 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR2T26A7PS240-DB | 功能描述:FPGA - 现场可编程门阵列 2304 LUT 326 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR2T26A7S208-DB | 功能描述:FPGA - 现场可编程门阵列 Use LatticeEC RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
发布紧急采购，3分钟左右您将得到回复。