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| 型号： | OR2T40A6BC432I-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 900 CLBS, 43200 GATES, PBGA432 |
| 封装： | EBGA-432 |
| 文件页数： | 114/196页 |
| 文件大小： | 3475K |
| 代理商： | OR2T40A6BC432I-DB |
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24
Lattice Semiconductor
Data Sheet
ORCA Series 2 FPGAs
January 2003
Programmable Logic Cells (continued)
PLC Architectural Description
reects the PFU, the lines, and the CIPs. A discussion
of each of the letters in the drawing follows.
A. These are switching lines which give the router exi-
bility. In general switching theory, the more levels of
indirection there are in the routing, the more routable
the network is. The switching lines can also connect
to adjacent PLCs.
The switching lines provide direct connections to
PLCs directly to the top, bottom, left, and right, with-
out using other routing resources. The ability to dis-
able this connection between PLCs is provided so
that each side of these connections can be used
exclusively as switching lines in their respective
PLC.
B. These CIPs connect the X1 routing. These are
located in the middle of the PLC to allow the block to
connect to either the left end of the horizontal X1 line
from the right or the right end of the horizontal X1
line from the left, or both. By symmetry, the same
principle is used in the vertical direction. The X1
lines are not twisted, making them suitable for data
paths.
C. This set of CIPs is used to connect the X1 and X4
nets to the switching lines or to other X1 and X4
nets. The CIPs on the major diagonal allow data to
be transmitted from X1 nets to the switching lines
without being scrambled. The CIPs on the major
diagonal also allow unscrambled data to be passed
between the X1 and X4 nets.
In addition to the major diagonal CIPs for the X1
lines, other CIPs provide an alternative entry path
into the PLC in case the rst one is already used.
The other CIPs are arrayed in two patterns, as
shown. Both of these patterns start with the main
diagonal, but the extra CIPs are arrayed on either a
parallel diagonal shifted by one or shifted by two
(modulo the size of the vertical bus (5)). This allows
any four application nets incident to the PLC corner
to be transferred to the ve switching lines in that
corner. Many patterns of ve nets can also be trans-
ferred.
D. The X4 lines are twisted at each PLC. One of the
four X4 lines is broken with a CIP, which allows a sig-
nal to be routed a distance of four PLCs in any direc-
tion on a single line without an intermediate CIP. The
X4 lines are less populated with CIPs than the X1
lines to increase their speed. A CIP can be enabled
to extend an X4 line four more PLCs, and so on.
For example, if an application signal is routed onto
HX4[4] in a PLC, it appears on HX4[5] in the PLC to
the right. This signal step-up continues until it
reaches HX4[7], two PLCs later. At this point, the
user can break the connection or continue the signal
for another four PLCs.
E. These symbols are bidirectional buffers (BIDIs).
There are four BIDIs per PLC, and they provide sig-
nal amplication as needed to decrease signal
delay. The BIDIs are also used to transmit signals on
XL lines.
F. These are the BIDI and BIDIH controllers. The 3-
state control signal can be disabled. They can be
congured as active-high or active-low indepen-
dently of each other.
G. This set of CIPs allows a BIDI to get or put a signal
from one set of switching lines on each side. The
BIDIs can be accessed by the switching lines. These
CIPs allow a nibble of data to be routed though the
BIDIs and continue to a subsequent block. They also
provide an alternative routing resource to improve
routability.
H. These CIPs are used to take data from/to the BIDIs
to/from the XL lines. These CIPs have been opti-
mized to allow the BIDI buffers to drive the large load
usually seen when using XL lines.
I. Each latch/FF can accept data: from an LUT output;
from a direct data input signal from general routing;
or, as in the case of PLCs located in the two rows
(columns) adjacent to PICs, directly from the pad. In
addition, the LUT outputs can bypass the latches/
FFs completely and output data on the general rout-
ing resources. The four inputs shown are used as
the direct input to the latches/FFs from general rout-
ing resources. If the LUT is in memory mode, the
four inputs WD[3:0] are the data input to the mem-
ory.
相关PDF资料 |
PDF描述 |
|---|---|
| OR2T40A7BC432-DB | FPGA, 900 CLBS, 43200 GATES, PBGA432 |
| OR2C08A-2B256 | FPGA, 196 CLBS, 7000 GATES, PBGA256 |
| OR2C08A-3B256 | FPGA, 196 CLBS, 7000 GATES, PBGA256 |
| OR2C08A-4B256 | FPGA, 196 CLBS, 7000 GATES, PBGA256 |
| OR2C08A-2B256I | FPGA, 196 CLBS, 7000 GATES, PBGA256 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| OR2T40A6PS208-DB | 功能描述:FPGA - 现场可编程门阵列 3600 LUT 326 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR2T40A6PS208I-DB | 功能描述:FPGA - 现场可编程门阵列 3600 LUT 326 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR2T40A6PS240DB | 制造商:ORCA 功能描述:NEW |
| OR2T40A6PS240-DB | 功能描述:FPGA - 现场可编程门阵列 3600 LUT 326 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| OR2T40A6PS240I-DB | 功能描述:FPGA - 现场可编程门阵列 3600 LUT 326 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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