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参数资料
型号： ORSO42G5-2BM484I
厂商： Lattice Semiconductor Corporation
文件页数： 15/153页
文件大小： 0K
描述： IC FPSC TRANSCEIVER 4CH 484-BGA
产品变化通告： Product Discontinuation 01/Aug/2011
标准包装： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
111
Input Eye-Mask Characterization
Figure 51 provides an eye-mask characterization of the SERDES receiver input. The eye-mask is specied below
for two different eye-mask heights. It provides guidance on a number of input parameters, including signal ampli-
tude and rise time limits, noise and jitter limits, and P and N input skew tolerance. Almost all detrimental character-
istics of transmit signal and the interconnection link design result in eye-closure. This, combined with the eye-
opening limitations of the line receiver, can provide a good indication of a link’s ability to transfer data error-free.
The Clock and Data Recovery (CDR) portion of the ORSO42G5 and ORSO82G5 SERDES receiver has the ability
to lter incoming signal jitter that is below the clock recovery PLL bandwidth (about 3 MHz). The eye-mask speci-
cations of Table 45 are for jitter frequencies above the PLL bandwidth of the CDR, which is a worst case condition.
When jitter occurs at frequencies below the PLL bandwidth, the receiver jitter tolerance is signicantly better. For
this case error-free data detection can occur even with a completely closed eye-mask.
Figure 51. Receive Data Eye-Diagram Template (Differential)
Table 45. Receiver Eye-Mask Specications1
Parameter
Conditions
Value
Unit
Input Data
Eye Opening Width (H)@ 2.7Gbps
V=175 mV diff
1
0.55
UIP-P
Eye Opening Width (T)@ 2.7Gbps
V=175 mV diff
1
0.15
UIP-P
Eye Opening Width (H)@ 2.7Gbps
V=600 mV diff
1
0.35
UIP-P
Eye Opening Width (T)@ 2.7Gbps
V=600 mV diff
1
0.10
UIP-P
Eye Opening Width (H)@ 2.5Gbps
V=175 mV diff
1
0.42
UIP-P
Eye Opening Width (T)@ 2.5Gbps
V=175 mV diff
1
0.15
UIP-P
Eye Opening Width (H)@ 2.5Gbps
V=600 mV diff
1
0.33
UIP-P
Eye Opening Width (T)@ 2.5Gbps
V=600 mV diff
1
0.10
UIP-P
1. With PRBS 2^7-1 data pattern, 10 MHz sinusoidal jitter, all channels operating, FPGA logic active, REFCLK jitter
of 30 ps., TA = 0
oC to 85oC, 1.425V to 1.575V supply.
H
V
1.2 V
UI
T
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