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参数资料
型号： OV09121-C00A
厂商： Electronic Theatre Controls, Inc.
英文描述： OV9625 Color CMOS SXGA (1.3 MPixel) CAMERACHIP OV9121 B&W CMOS SXGA (1.3 MPixel) CAMERACHIP
中文描述： OV9625彩色CMOS SXGA（1.3万像素）的CameraChip OV9121乙
文件页数： 27/30页
文件大小： 361K
代理商： OV09121-C00A
6
Proprietary to OmniVision Technologies
Version 1.3, September 15, 2003
OV9625/OV9121
CMOS SXGA (1.3 MPixel) CAMERACHIP
Omni
ision
Digital Video Port
MSB/LSB Swap
OV9625/OV9121 has a 10-bit digital video port. The MSB
and LSB can be swapped with the control registers.
Figure 11 shows some examples of connections with
external devices.
Figure 11 Connection Examples
D7
D6
D5
D4
D3
D2
D1
LSB D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
MSB D0
D2
D3
D4
D5
D6
D7
D8
D9
External
Device
OV9625
(OV9121)
External
Device
OV9625
(OV9121)
MSB D9
D8
D9
D8
LSB D9
D8
D0
D1
Default 10-bit Connection
Swap 10-bit Connection
D7
D6
D5
D4
D3
D2
D1
LSB D0
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
MSB D0
D0
D1
D2
D3
D4
D5
D6
D7
External
Device
OV9625
(OV9121)
External
Device
OV9625
(OV9121)
MSB D9
D8
D7
D6
LSB D9
D8
Default 8-bit Connection
Swap 8-bit Connection
Line/Pixel Timing
The
OV9625/OV9121
digital
video
port
can
be
programmed to work in either master or slave mode.
In both master and slave modes, pixel data output is
synchronous with PCLK (or MCLK if port is a slave),
HREF and VSYNC. The default PCLK edge for valid data
is the negative edge but may be programmed with register
COMK[4] (see “COMK” on page 22) for the positive edge.
Basic line/pixel output timing is illustrated in Figure 14 and
Figure 15.
To minimize image capture circuitry and conserve
memory space, PCLK output can be programmed with
register COMK[5] (see “COMK” on page 22) to be
qualified by the active video period as defined by the
HREF signal. See Figure 12 for details.
Figure 12 PCLK Output Only at Valid Pixels
Pixel Output Pattern
Table 1
shows
the
output
data
order
from
the
OV9625/OV9121. The data output sequence following the
first HREF and after VSYNC is: B0,0 G0,1 B0,2 G0,3…
B0,1278 G0,1279. After the second HREF, the output is G1,0
R1,1 G1,2 R1,3… G1,1278 R1,1279…, etc. If the
OV9625/OV9121
is
programmed
to
output
VGA
resolution data, horizontal and vertical sub-sampling will
occur. The default output sequence for the first line of
output will be: B0,0 G0,1 B0,4 G0,5… B0,1276 G0,1277. The
second line of output will be: G1,0 R1,1 G1,4 R1,5… G1,1276
R1,1277.
Table 1
Data Pattern
R/C
0
1
2
3
. . .
1278
1279
0B0,0
G0,1
B0,2
G0,3
. . .
B0,1278
G0,1279
1G1,0
R1,1
G1,2
R1,3
. . .
G1,1278
R1,1279
2B2,0
G2
B2,2
G2,3
. . .
B2,1278
G2,1279
3G3,0
R3,1
G3,2
R3,3
. . .
G3,1278
R3,1279
.
1022
B1022,0 G1022,1 B1022,2 G1022,3
B1022,1278 G1022,1279
1023
G1023,0 R1023,1 G1023,2 R1023,3
G1023,1278 R1023,1279
VSYNC
PCLK
HREF
PCLK
PCLK active edge positive
PCLK active edge negative
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