参数资料
型号: P60ARM-IG
厂商: Zarlink Semiconductor Inc.
英文描述: Low power, general purpose 32-bit RISC microprocessor
中文描述: 低功耗,通用32位RISC微处理器
文件页数: 10/120页
文件大小: 1275K
代理商: P60ARM-IG
P60ARM-B
6
DBE
I
Data bus enable. When
When
DBE
goes HIGH these output drivers are enabled.
DMA and so on.
DBE
is LOW the write data register output drivers are disabled.
DBE
facilitates data bus sharing for
LATEABT
I
Late
HIGH (Late
back. When it is LOW (Early abort) the modified base register is not written back.
must not be changed during the execution of a data access instruction where abort is active.
It is recommended that the Late
abort scheme be used where possible as this scheme will be
used in future ARM processors.
abort. This signal controls the action of the processor on an
abort) the modified base register of an
abort exception. When it is
aborted LDR or STR instruction is written
LATEABT
LOCK
OS8
Locked operation. When
access, and the memory controller must wait until
device to access the memory.
the duration of the locked memory accesses. It is active only during the data swap (SWP)
instruction.
LOCK
is HIGH, the processor is performing a òlockedó memory
LOCK
goes LOW before allowing another
LOCK
changes while
MCLK
is HIGH, and remains HIGH for
MCLK
I
Memory clock input. This clock times all ARM60 memory accesses and internal operations.
The clock has two distinct phases -
phase 1
in which
MCLK
(and
nWAIT
) is HIGH. The clock may be stretched indefinitely in either phase to
allow access to slow peripherals or memory. Alternatively, the
with a free running
MCLK
to achieve the same effect.
MCLK
is LOW and
phase 2
in which
nWAIT
input may be used
nBW
OS8
Not byte/word. This is an output signal used by the processor to indicate to the external
memory system when a data transfer of a byte length is required. The signal is HIGH for
word transfers and LOW for byte transfers and is valid for both read and write cycles. The
signal will become valid during phase 2 of the cycle before the one in which the transfer will
take place. It will remain stable throughout phase 1 of the transfer cycle.
nCPI
O4
Not Coprocessor instruction. When ARM60 executes a coprocessor instruction, it will take
this output LOW and wait for a response from the coprocessor. The action taken will depend
on this response, which the coprocessor signals on the
CPA
and
CPB
inputs.
nFIQ
I
Not fast interrupt request. This is an asynchronous interrupt request to the processor which
causes it to be interrupted if taken LOW when the appropriate enable in the processor is
active. The signal is level sensitive and must be held LOW until a suitable response is
received from the processor.
nIRQ
I
Not interrupt request. As
to interrupt the processor when the appropriate enable is active.
nFIQ
, but with lower priority. May be taken LOW asynchronously
nMREQ
O4
Not memory request. This signal, when LOW, indicates that the processor requires memory
access during the following cycle. The signal becomes valid during phase 1, remaining valid
through phase 2 of the cycle preceding that to which it refers.
nOPC
O4
Not op-code fetch. When LOW this signal indicates that the processor is fetching an
instruction from memory; when HIGH, data (if present) is being transferred. The signal
becomes valid during phase 2 of the previous cycle, remaining valid through phase 1 of the
referenced cycle.
Name
Type
Description
Table 1: Signal Description
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