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| 型号： | P83C180 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(带DDC接口，同步监测和同步处理的监视器微控制器) |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP42 |
| 封装： | 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42 |
| 文件页数： | 47/84页 |
| 文件大小： | 420K |
| 代理商： | P83C180 |
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1997 Dec 12
47
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
17.3
DDC1 protocol
The DDC1 is a primitive interface, but adopted by many
monitor models and PC hosts. It is a point-to-point
interface. The monitor is always set to ‘Transmit only’
mode. In the initialization phase, 9 clock cycles on the
VCLK pin will be given for the internal synchronization.
During this period, the SDA pin will be kept in the
high-impedance state. By default, bit ‘DDC1enable’ is
reset as logic 0. It is advised to move the EDID data to the
RAM buffer before enabling DDC1. To activate the DDC1
interface, DDC1enable flag is set to logic 1 and it is taken
as granted that Mode flag M0 is set at logic 0. If SWENB is
kept at the default value logic 0, the RAM buffer will be tied
to the DDC1 protocol. The allocated size from the RAM
buffer is decided by the flag EX_DAT. If EX_DAT is LOW,
only 128 bytes are reserved to store DDC1 EDID data. The
upper part (locations 128 to 255) is still available to the
system. If EX_DAT is HIGH, the entire 256 bytes of the
RAM buffer are dedicated to the usage of DDC1 operation.
The hardware mechanism will automatically move new
data from the defined RAM buffer to the hold register of the
transmitter with the aid of the address pointer DDCADR.
Within the range of DDC1 RAM buffer, the function of the
post increment is executed. If the upper limit is reached,
the address pointer DDCADR will wrap around to 00H.
However, if EX_DAT = LOW, the lower part is occupied by
the DDC1 operation and the upper part is still free to the
system. Nevertheless, the effect of the post increment just
applies to the part related to the DDC1 operation. In other
words, the system program is still able to address the
locations from 128 to 255 in the RAM buffer through the
MOVX command but without the facility of the post
increment; e.g. in case EX_DAT = LOW and
SWENB = LOW, the system program might read one data
byte from address 200 of the RAM buffer by the following
procedure:
MOV R0, #200; MOVX A, @R0.
The address pointer DDCADR is tied to the DDC1
transmitter here. To avoid the interference to the content
of DDCADR, it has to address the RAM buffer through the
MOVX command. While EX_DAT = HIGH, the entire RAM
buffer is covered by the pointing range of the address
pointer DDCADR, with the capability of the post increment;
no matter whether the access is done by DDC1 related
hardware (SWENB = 0) or software (SWENB = 1).
If SWENB is set at logic 1, then after the valid
synchronization, the DDC1 interrupt will be invoked
(interrupt vector address 002BH). The service routine
should fill the hold register DDCDAT (SFR address 9FH)
with the first data byte either from the internal ROM (part
of the system ROM) or from the RAM buffer. In the latter
case, the address pointer DDCADR will provide the benefit
of the post increment for the service routine to read/write
the DDC1 EDID data area. This action must be finished
within 40
μ
s (40 machine cycles in 12 MHz system clock).
DDC1_int flag must be cleared by software before it
returns from service routine. On the rising edge of the 10th
clock cycle, the device will output the first valid data bit
which should be the most significant bit of a byte.
The following data is also transmitted on the SDA pin in
8 bits per byte format. Each byte is followed by a 9th clock
pulse during which time SDA is left high-impedance and
either the hardware mechanism (SWENB = 0) or the
service routine (SWENB = 1) will update the hold register.
The data bit is output on the rising edge of VCLK, the most
significant bit first. The address pointer is initialized at 00H.
After writing a data byte to the hold register through
hardware or software, it will be incremented by one
automatically. If the address reaches 127 (EX_DAT = 0) or
255 (EX_DAT = 1) the address pointer will wrap around to
the first location: 00H. Nevertheless, it is possible for CPU
(in software mode, i.e. SWENB = 1) to write any desired
address to the address pointer to proceed random access.
The transaction in DDC1 protocol is shown in Fig.25.
If DDC1 hardware mode is used, the following DDC1
operation steps are recommended:
1.
Reset DDC1enable (by default DDC1enable is cleared
to LOW after power-on reset).
2.
Set SWENB to HIGH.
3.
Depending on the data size of EDID data, set EX_DAT
to LOW (128 bytes) or HIGH (256 bytes).
4.
Use substantial moving commands (DDCADR,
RAMBUF involved) to move the entire EDID data to
RAM buffer.
5.
Reset SWENB to LOW.
6.
Reset DDCADR to 00H.
7.
Set DDC1enable to HIGH enabling the DDC1
hardware; during the synchronization phase (the first 9
VCLK clocks) the first data byte will be loaded into the
shift register of the transmitter through the hold
register.
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