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| 型号： | P83C180 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(带DDC接口，同步监测和同步处理的监视器微控制器) |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP42 |
| 封装： | 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42 |
| 文件页数： | 74/84页 |
| 文件大小： | 420K |
| 代理商： | P83C180 |
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1997 Dec 12
74
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
Notes
1.
2.
For the DDC2 Mode (bidirectional I
2
C-bus mode), refer to the standard I
2
C-bus specification.
The actual sync width has to fulfil both requirements, maximum pulse width t
W(HSYNC)
= 8.0
μ
s and maximum duty
cycle H
DCYC
of 25%, at the same time.
The polarity of the horizontal sync pulse is said to be positive if the HIGH period is shorter than the LOW period.
The actual sync width has to fulfil both requirements, maximum pulse width t
W(VSYNC)
= 24 horizontal line periods
and maximum duty cycle V
DCYC
of 25%, at the same time.
3.
4.
Composite Sync Input for the Mode Detection; see Figs
38
and
39
T
EQ(CSYNC)
equalizing pulse period for CSYNC
input
equalizing pulse width for CSYNC
input
equalizing pulses plus the VSYNC
interval
0.5
note 5
t
WEQ(CSYNC)
0.5
note 6
NEQ
30
note 5
Horizontal and Vertical Pulse Generation; see Figs
40
and
41
T
H(free)
t
WH(free)
t
or(HSYNC)
t
of(HSYNC)
t
d(in-out)(HSYNC)
t
dmax(HSYNCm)
horizontal pulse period in free running
horizontal pulse width in free running
HSYNC output pulse rise time
HSYNC output pulse fall time
HSYNC output delay to input
HSYNC output maximum delay after
missing HSYNC
HSYNC output substitution pulse width
t
d(HSYNC-CLAMP)
CLAMP pulse delay to HSYNC input
t
W(CLAMP)
CLAMP pulse width
T
V(free)
vertical pulse period in free running
t
WV(free)
vertical pulse width in free running
t
or(VSYNC)
VSYNC output pulse rise time
t
of(VSYNC)
VSYNC output pulse fall time
t
d(in-out)(VSYNC)
VSYNC output delay to input
t
dmax(VSYNCm)
VSYNC output maximum delay after
missing VSYNC
t
W(VSYNCsub)
VSYNC output substitution pulse width
10
0.4
30
24
31
26
66
2.5
32
28
100
350
μ
s
μ
s
ns
ns
ns
ns
t
W(HSYNCsub)
0
0.4
22
24
24
27
2.5
125
2.5
2048
32
26
30
250
1
μ
s
ns
μ
s
note 5
note 5
ns
ns
ns
note 5
16
note 5
Slope control port
t
tLH(sce)
LOW-to-HIGH transition delay while
slope control enabled
HIGH-to-LOW transition delay while
slope control enabled
LOW-to-HIGH propagation delay while
slope control disabled
HIGH-to-LOW propagation delay while
slope control disabled
0.1V
DD
to 0.9V
DD
; note 7
25
100
ns
t
tHL(sce)
0.9V
DD
to 0.1V
DD
; note 7
25
100
ns
t
PLH(scd)
0.1V
DD
to 0.9V
DD
;
load = 50 pF
0.9V
DD
to 0.1V
DD
;
load = 50 pF
10
ns
t
PHL(scd)
10
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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