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| 型号： | P83C180 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(带DDC接口，同步监测和同步处理的监视器微控制器) |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP42 |
| 封装： | 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42 |
| 文件页数： | 48/84页 |
| 文件大小： | 420K |
| 代理商： | P83C180 |
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1997 Dec 12
48
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
Fig.25 Transmission protocol in DDC1 interface.
handbook, full pagewidth
DDC1_INT
DDC1 enable
MGG032
1
2
3
4
5
6
7
8
9
1
2
3
1
4
5
6
7
8
9
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
BIT
0
BIT
7
High Z
00
01
11
01
11
01
SCL
SDA
VCLK
tsu(DDC1)
tVCLKH
tVCLKL
tDOV
High Z
17.4
DDC2B protocol
The DDC2B construction is based on the Philips I
2
C-bus
interface. However, in the level of DDC2B, PC host is fixed
as the master and the monitor is always regarded as the
slave. Both master and slave can be operated as a
transmitter or receiver, but the master device determines
which mode is activated. For details of the I
2
C-bus
interface, please refer to the Philips publication
“The I
2
C-bus and how to use it”ordering number
9398 393 40011 and/or the “Data Handbook IC20”
In the P83C880, one more pair of I
2
C-bus pins SCL1,
SDA1 and an I
2
C-bus hardware interface logic are
dedicated to perform DDC2B/DDC2B+/DDC2AB
protocols. The built-in address pointer mentioned in
Section 17.3 can be used to speed up the processing of
service routines for the access of the internal ROM or a
dedicated RAM buffer.
According to the DDC2B specification:
A0H (for write mode) and
A1H (for read mode),
are assigned as the default address of monitors.
The reception of the incoming data in write mode or the
updating of the outgoing data in read mode should be
finished within the specified time limit. However, it is not
necessary for EDID data to be stored on-chip. It is also
possible to have access to the external EEPROM/ROM
through another set of I
2
C-bus interface and pre-store
those data in the RAM buffer. If software on the slave side
cannot react to the master in time, based on I
2
C-bus
protocol, SCL pin can be stretched LOW to inhibit the
further action from the master. The transaction can be
proceeded in either byte or burst format.
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