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参数资料
| 型号： | P89LPC9221FN,112 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 33/46页 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU FLASH 8K 20-DIP |
| 标准包装： | 18 |
| 系列： | LPC900 |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 18MHz |
| 连通性： | I²C，UART/USART |
| 外围设备： | 欠压检测/复位，LED，POR，PWM，WDT |
| 输入/输出数： | 18 |
| 程序存储器容量： | 8KB（8K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 256 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.4 V ~ 3.6 V |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 20-DIP（0.300"，7.62mm） |
| 包装： | 管件 |
| 配用： | 622-1014-ND - BOARD FOR LPC9XX TSSOP 622-1010-ND - BOARD FOR LPC922 TSSOP 622-1008-ND - BOARD FOR LPC9103 10-HVSON 622-1006-ND - SOCKET ADAPTER BOARD 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X |
| 其它名称： | 568-3224-5 935277592112 P89LPC9221FN |
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Philips Semiconductors
P89LPC920/921/922/9221
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 08 — 15 December 2004
39 of 46
9397 750 14469
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1]
Parameters are valid over operating temperature range unless otherwise specied. Parts are tested to 2 MHz, but are guaranteed to
operate down to 0 Hz.
[2]
When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until VDD has reached its specied level. When system power is removed VDD will fall below the
minimum specied operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout
detect circuit may be required to hold the device in reset when VDD falls below the minimum specied operating voltage.
Table 10:
AC characteristics
VDD = 3.0 V to 3.6 V unless otherwise specied.
Symbol
Parameter
Conditions
Variable clock
fosc =18MHz
Unit
Min
Max
Min
Max
fRCOSC
internal RC oscillator frequency
(nominal f = 7.3728 MHz)
trimmed to
±1%
at Tamb =25 °C
7.189
7.557
7.189
7.557
MHz
fWDOSC
internal Watchdog oscillator
frequency (nominal f = 400 kHz)
320
520
320
520
kHz
fosc
oscillator frequency
[2] 0
18
-
MHz
tCLCL
clock cycle
see Figure 13
55
-
ns
fCLKP
CLKLP active frequency
0
8
-
MHz
Glitch lter
glitch rejection, P1.5/RST pin
-
50
-
50
ns
signal acceptance, P1.5/RST pin
125
-
125
-
ns
glitch rejection, any pin except
P1.5/RST
-
15
-
15
ns
signal acceptance, any pin except
P1.5/RST
50
-
50
-
ns
External clock
tCHCX
HIGH time
see Figure 13
22
tCLCL tCLCX
22
-
ns
tCLCX
LOW time
see Figure 13
22
tCLCL tCHCX
22
-
ns
tCLCH
rise time
see Figure 13
-5
-
5
ns
tCHCL
fall time
see Figure 13
-5
-
5
ns
Shift register (UART mode 0)
tXLXL
serial port clock cycle time
16 tCLCL
-
888
-
ns
tQVXH
output data set-up to clock rising
edge
13 tCLCL
-
722
-
ns
tXHQX
output data hold after clock rising
edge
-tCLCL + 20
-
75
ns
tXHDX
input data hold after clock rising edge
-
0
-
0
ns
tDVXH
input data valid to clock rising edge
150
-
150
-
ns
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