参数资料
型号: P89LPC9221FN,112
厂商: NXP Semiconductors
文件页数: 5/46页
文件大小: 0K
描述: IC 80C51 MCU FLASH 8K 20-DIP
标准包装: 18
系列: LPC900
核心处理器: 8051
芯体尺寸: 8-位
速度: 18MHz
连通性: I²C,UART/USART
外围设备: 欠压检测/复位,LED,POR,PWM,WDT
输入/输出数: 18
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 2.4 V ~ 3.6 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 20-DIP(0.300",7.62mm)
包装: 管件
配用: 622-1014-ND - BOARD FOR LPC9XX TSSOP
622-1010-ND - BOARD FOR LPC922 TSSOP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1006-ND - SOCKET ADAPTER BOARD
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名称: 568-3224-5
935277592112
P89LPC9221FN
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Philips
Semiconductor
s
P89LPC920/921/922/9221
8-bit
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13
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46
[1]
All ports are in input only (high impedance) state after power-up.
[2]
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any are written while BRGEN = 1, the result is unpredictable.
[3]
The RSTSRC register reects the cause of the P89LPC920/921/922/9221 reset. Upon a power-up reset, all reset source ags are cleared except POF and BOF; the power-on
reset value is xx110000.
[4]
After reset, the value is 111001x1, i.e., PRE2-PRE0 are all ‘1’, WDRUN = 1 and WDCLK = 1. WDTOF bit is ‘1’ after watchdog reset and is ‘0’ after power-on reset. Other resets will
not affect WDTOF.
[5]
On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[6]
The only reset source that affects these SFRs is power-on reset.
TRIM
Internal oscillator trim register
96H
-
ENCLK
TRIM.5
TRIM.4
TRIM.3
TRIM.2
TRIM.1
TRIM.0
WDCON
Watchdog control register
A7H
PRE2
PRE1
PRE0
-
WDRUN
WDTOF
WDCLK
WDL
Watchdog load
C1H
FF
11111111
WFEED1
Watchdog feed 1
C2H
WFEED2
Watchdog feed 2
C3H
Table 4:
Special function registers…continued
* indicates SFRs that are bit addressable.
Name
Description
SFR
addr.
Bit functions and addresses
Reset value
MSB
LSB
Hex
Binary
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