参数资料
型号: P89LPC9221FN,112
厂商: NXP Semiconductors
文件页数: 6/46页
文件大小: 0K
描述: IC 80C51 MCU FLASH 8K 20-DIP
标准包装: 18
系列: LPC900
核心处理器: 8051
芯体尺寸: 8-位
速度: 18MHz
连通性: I²C,UART/USART
外围设备: 欠压检测/复位,LED,POR,PWM,WDT
输入/输出数: 18
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 2.4 V ~ 3.6 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 20-DIP(0.300",7.62mm)
包装: 管件
配用: 622-1014-ND - BOARD FOR LPC9XX TSSOP
622-1010-ND - BOARD FOR LPC922 TSSOP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1006-ND - SOCKET ADAPTER BOARD
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名称: 568-3224-5
935277592112
P89LPC9221FN
Philips Semiconductors
P89LPC920/921/922/9221
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 08 — 15 December 2004
14 of 46
9397 750 14469
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.
Functional description
Remark: Please refer to the
P89LPC920/921/922/9221 User’s Manual for a more
detailed functional description.
8.1 Enhanced CPU
The P89LPC920/921/922/9221 uses an enhanced 80C51 CPU which runs at 6 times
the speed of standard 80C51 devices. A machine cycle consists of two CPU clock
cycles, and most instructions execute in one or two machine cycles.
8.2 Clocks
8.2.1
Clock denitions
The P89LPC920/921/922/9221 device has several internal clocks as dened below:
OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four
clock sources (see Figure 5) and can also be optionally divided to a slower frequency
Note: fosc is dened as the OSCCLK frequency.
CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per
machine cycle, and most instructions are executed in one to two machine cycles (two
or four CCLK cycles).
RCCLK — The internal 7.373 MHz RC oscillator output.
PCLK — Clock for the various peripheral devices and is CCLK/2
8.2.2
CPU clock (OSCCLK)
The P89LPC920/921/922/9221 provides several user-selectable oscillator options in
generating the CPU clock. This allows optimization for a range of needs from high
precision to lowest possible cost. These options are congured when the FLASH is
programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an
oscillator using an external crystal, or an external clock source. The crystal oscillator
can be optimized for low, medium, or high frequency crystals covering a range from
20 kHz to 12 MHz.
8.2.3
Low speed oscillator option
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic
resonators are also supported in this conguration.
8.2.4
Medium speed oscillator option
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic
resonators are also supported in this conguration.
8.2.5
High speed oscillator option
This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic
resonators are also supported in this conguration. When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be enabled. An
external circuit is required to hold the device in reset at power-up until VDD has
reached its specied level. When system power is removed VDD will fall below
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