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| 型号： | P89LPC932A1FDH |
| 厂商： | NXP Semiconductors N.V. |
| 元件分类： | 8位微控制器 |
| 英文描述： | 8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROM |
| 封装： | P89LPC932A1FDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html<1<week 47, 2004,;P89LPC932A1FDH/G<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1. |
| 文件页数： | 18/64页 |
| 文件大小： | 319K |
| 代理商： | P89LPC932A1FDH |
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P89LPC932A1_3
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 12 March 2007
25 of 64
NXP Semiconductors
P89LPC932A1
8-bit microcontroller with accelerated two-clock 80C51 core
After power-up this input will function either as an external reset input or as a digital input
as dened by the RPE bit. Only a power-up reset will temporarily override the selection
dened by RPE bit. Other sources of reset will not override the RPE bit.
Reset can be triggered from the following sources:
External reset pin (during power-up or if user congured via UCFG1).
Power-on detect.
Brownout detect.
Watchdog timer.
Software reset.
UART break character detect reset.
For every reset source, there is a ag in the Reset Register, RSTSRC. The user can read
this register to determine the most recent reset source. These ag bits can be cleared in
software by writing a logic 0 to the corresponding bit. More than one ag bit may be set:
During a power-on reset, both POF and BOF are set but the other ag bits are
cleared.
For any other reset, previously set ag bits that have not been cleared will remain set.
7.16.1 Reset vector
Following reset, the P89LPC932A1 will fetch instructions from either address 0000H or
the Boot address. The Boot address is formed by using the Boot Vector as the high byte of
the address and the low byte of the address = 00H.
The Boot address will be used if a UART break reset occurs, or the non-volatile Boot
Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see
P89LPC932A1
User manual). Otherwise, instructions will be fetched from address 0000H.
7.17 Timers/counters 0 and 1
The P89LPC932A1 has two general purpose counter/timers which are upward compatible
with the standard 80C51 Timer 0 and Timer 1. Both can be congured to operate either as
timers or event counter. An option to automatically toggle the T0 and/or T1 pins upon timer
overow has been added.
In the ‘Timer’ function, the register is incremented every machine cycle.
In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin, T0 or T1. In this function, the external input is sampled
once during every machine cycle.
Timer 0 and Timer 1 have ve operating modes (modes 0, 1, 2, 3 and 6). Modes 0, 1, 2
and 6 are the same for both Timers/Counters. Mode 3 is different.
7.17.1 Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a divide-by-32 prescaler. In this mode, the Timer register is congured as a
13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| P89LPC932A1FDH,512 | 功能描述:8位微控制器 -MCU 80C51 8K FL 768B RAM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| P89LPC932A1FDH,529 | 功能描述:8位微控制器 -MCU 8K FL/768B RAM/512B EE/CCU RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| P89LPC932A1FDH512 | 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 80C51 18MHZ TSSOP-28 |
| P89LPC932A1FHN | 制造商:NXP Semiconductors 功能描述:MCU 8BIT 80C51 8K FLASH HVQFN-28 |
| P89LPC932A1FHN,151 | 功能描述:8位微控制器 -MCU 80C51 8K FL 768B RAM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
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