参数资料
型号: P89LPC935FA,129
厂商: NXP Semiconductors
文件页数: 47/77页
文件大小: 0K
描述: IC 80C51 MCU FLASH 8K 28-PLCC
产品培训模块: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
标准包装: 37
系列: LPC900
核心处理器: 8051
芯体尺寸: 8-位
速度: 12MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,LED,POR,PWM,WDT
输入/输出数: 26
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
EEPROM 大小: 512 x 8
RAM 容量: 768 x 8
电压 - 电源 (Vcc/Vdd): 2.4 V ~ 3.6 V
数据转换器: A/D 8x8b; D/A 2x8b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-PLCC
包装: 管件
产品目录页面: 706 (CN2011-ZH PDF)
配用: 622-1014-ND - BOARD FOR LPC9XX TSSOP
622-1006-ND - SOCKET ADAPTER BOARD
568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
622-1002-ND - USB IN-CIRCUIT PROG LPC9XX
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY
其它名称: 568-1287-5
935274628129
P89LPC935FA-S
P89LPC933_934_935_936
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 12 January 2011
51 of 77
NXP Semiconductors
P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
In addition, IAP operations can be accomplished through the use of four SFRs consisting
of a control/status register, a data register, and two address registers. Additional details
may be found in the P89LPC933/934/935/936 User manual.
8.28.8 ISP
ISP is performed without removing the microcontroller from the system. The ISP facility
consists of a series of internal hardware resources coupled with internal firmware to
facilitate remote programming of the P89LPC933/934/935/936 through the serial port.
This firmware is provided by Philips and embedded within each P89LPC933/934/935/936
device. The Philips ISP facility has made ISP in an embedded application possible with a
minimum of additional expense in components and circuit board area. The ISP function
uses five pins (VDD, VSS, TXD, RXD, and RST). Only a small connector needs to be
available to interface your application to an external circuit in order to use this feature.
8.28.9 Power-on reset code execution
The P89LPC933/934/935/936 contains two special flash elements: the boot vector and
the boot status bit. Following reset, the P89LPC933/934/935/936 examines the contents
of the boot status bit. If the boot status bit is set to zero, power-up execution starts at
location 0000H, which is the normal start address of the user’s application code. When
the boot status bit is set to a value other than zero, the contents of the boot vector are
used as the high byte of the execution address and the low byte is set to 00H.
Table 9 shows the factory default boot vector settings for these devices.
Remark: These settings are different than the original P89LPC932. Tools designed to
support the P89LPC933/934/935/936 should be used to program this device, such as
Flash Magic version 1.98, or later.
A factory-provided boot loader is preprogrammed into the address space indicated and
uses the indicated boot loader entry point to perform ISP functions. This code can be
erased by the user.
Remark: Users who wish to use this loader should take precautions to avoid erasing the
sector that contains this boot loader. Instead, the page erase function can be used to
erase the pages located in this sector which are not used by the boot loader.
A custom boot loader can be written with the boot vector set to the custom boot loader, if
desired.
Table 9.
Default boot vector values and ISP entry points
Device
Default
boot vector
Default
boot loader
entry point
Default boot loader
code range
Boot sector
range
P89LPC933
0FH
0F00H
0E00H to 0FFFH
0C00H to 0FFFH
P89LPC934
1FH
1F00H
1E00H to 1FFFH
1C00H to 1FFFH
P89LPC935
1FH
1F00H
1E00H to 1FFFH
1C00H to 1FFFH
P89LPC936
3FH
3F00H
3E00H to 3FFFH
3C00H to 3FFFH
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