参数资料
型号: P89LPC935FA,129
厂商: NXP Semiconductors
文件页数: 48/77页
文件大小: 0K
描述: IC 80C51 MCU FLASH 8K 28-PLCC
产品培训模块: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
标准包装: 37
系列: LPC900
核心处理器: 8051
芯体尺寸: 8-位
速度: 12MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,LED,POR,PWM,WDT
输入/输出数: 26
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
EEPROM 大小: 512 x 8
RAM 容量: 768 x 8
电压 - 电源 (Vcc/Vdd): 2.4 V ~ 3.6 V
数据转换器: A/D 8x8b; D/A 2x8b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-PLCC
包装: 管件
产品目录页面: 706 (CN2011-ZH PDF)
配用: 622-1014-ND - BOARD FOR LPC9XX TSSOP
622-1006-ND - SOCKET ADAPTER BOARD
568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
622-1002-ND - USB IN-CIRCUIT PROG LPC9XX
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY
其它名称: 568-1287-5
935274628129
P89LPC935FA-S
P89LPC933_934_935_936
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 12 January 2011
52 of 77
NXP Semiconductors
P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
8.28.10 Hardware activation of the boot loader
The boot loader can also be executed by forcing the device into ISP mode during a
power-on sequence (see the P89LPC933/934/935/936 User manual for specific
information). This has the same effect as having a non-zero status byte. This allows an
application to be built that will normally execute user code but can be manually forced into
ISP operation. If the factory default setting for the boot vector is changed, it will no longer
point to the factory preprogrammed ISP boot loader code. After programming the flash,
the status byte should be programmed to zero in order to allow execution of the user’s
application code beginning at address 0000H.
8.29 User configuration bytes
Some user-configurable features of the P89LPC933/934/935/936 must be defined at
power-up and therefore cannot be set by the program after start of execution. These
features are configured through the use of the flash byte UCFG1. Please see the
P89LPC933/934/935/936 User manual for additional details.
8.30 User sector security bytes
There are eight User Sector Security Bytes on the P89LPC933/934/935/936 device. Each
byte corresponds to one sector. Please see the P89LPC933/934/935/936 User manual for
additional details.
9.
A/D converter
9.1 General description
The P89LPC935/936 have two 8-bit, 4-channel multiplexed successive approximation
analog-to-digital converter modules sharing common control logic. The P89LPC933/934
have a single 8-bit, 4-channel multiplexed analog-to-digital converter and an additional
DAC module. A block diagram of the A/D converter is shown in Figure 23. Each A/D
consists of a 4-input multiplexer which feeds a sample-and-hold circuit providing an input
signal to one of two comparator inputs. The control logic in combination with the SAR
drives a digital-to-analog converter which provides the other input to the comparator. The
output of the comparator is fed to the SAR.
9.2 Features and benefits
Two (P89LPC935/936) 8-bit, 4-channel multiplexed input, successive approximation
A/D converters with common control logic (one A/D on the P89LPC933/934).
Four result registers for each A/D.
Six operating modes:
Fixed channel, single conversion mode.
Fixed channel, continuous conversion mode.
Auto scan, single conversion mode.
Auto scan, continuous conversion mode.
Dual channel, continuous conversion mode.
Single step mode.
Four conversion start modes:
Timer triggered start.
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