参数资料
型号: P89LPC9381FDH
厂商: NXP Semiconductors N.V.
元件分类: 8位微控制器
英文描述: 8-bit microcontroller with accelerated two-clock 80C51 core 4 kB 3 V byte-erasable flash with 10-bit ADC
封装: P89LPC9381FDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html<1<Always Pb-free,;
文件页数: 10/59页
文件大小: 286K
代理商: P89LPC9381FDH
P89LPC9381_1
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 8 September 2006
18 of 60
Philips Semiconductors
P89LPC9381
8-bit microcontroller with 10-bit ADC
The frequency of this clock output is 1
2 that of the CCLK. If the clock output is not needed
in Idle mode, it may be turned off prior to entering Idle, saving additional power.
7.4 On-chip RC oscillator option
The P89LPC9381 has a 6-bit TRIM register that can be used to tune the frequency of the
RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed
value to adjust the oscillator frequency to 7.373 MHz
± 1 % at room temperature.
End-user applications can write to the TRIM register to adjust the on-chip RC oscillator to
other frequencies.
7.5 Watchdog oscillator option
The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator
can be used to save power when a high clock frequency is not needed.
7.6 External clock input option
In this conguration, the processor clock is derived from an external source driving the
XTAL1/P3[1] pin. The rate may be from 0 Hz up to 18 MHz. The XTAL2/P3[0] pin may be
used as a standard port pin or a clock output. When using an oscillator frequency
above 12 MHz, the reset input function of P1[5] must be enabled. An external circuit
is required to hold the device in reset at power-up until VDD has reached its
specied level. When system power is removed VDD will fall below the minimum
specied operating voltage. When using an oscillator frequency above 12 MHz, in
some applications, an external brownout detect circuit may be required to hold the
device in reset when VDD falls below the minimum specied operating voltage.
Fig 4.
Block diagram of oscillator control
÷2
002aac463
RTC
ADC0
CPU
WDT
DIVM
CCLK
UART
OSCCLK
I2C-BUS
PCLK
TIMER 0 AND
TIMER 1
HIGH FREQUENCY
MEDIUM FREQUENCY
LOW FREQUENCY
XTAL1
XTAL2
RC
OSCILLATOR
WATCHDOG
OSCILLATOR
(7.3728 MHz
± 1 %)
PCLK
RCCLK
SPI
(400 kHz + 30 %
20 %)
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