参数资料
型号: P89LPC9381FDH
厂商: NXP Semiconductors N.V.
元件分类: 8位微控制器
英文描述: 8-bit microcontroller with accelerated two-clock 80C51 core 4 kB 3 V byte-erasable flash with 10-bit ADC
封装: P89LPC9381FDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html<1<Always Pb-free,;
文件页数: 18/59页
文件大小: 286K
代理商: P89LPC9381FDH
P89LPC9381_1
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 8 September 2006
25 of 60
Philips Semiconductors
P89LPC9381
8-bit microcontroller with 10-bit ADC
7.16 Reset
The P1[5]/RST pin can function as either an active-LOW reset input or as a digital input,
P1[5]. The RPE (Reset Pin Enable) bit in UCFG1, when set to ‘1’, enables the external
reset input function on P1[5]. When cleared, P1[5] may be used as an input pin.
Remark: During a power-up sequence, The RPE selection is overridden and this pin will
always functions as a reset input. An external circuit connected to this pin should not
hold this pin LOW during a power-on sequence as this will keep the device in reset.
After power-up this input will function either as an external reset input or as a digital input
as dened by the RPE bit. Only a power-up reset will temporarily override the selection
dened by RPE bit. Other sources of reset will not override the RPE bit.
Reset can be triggered from the following sources:
External reset pin (during power-up or if user congured via UCFG1);
Power-on detect;
Brownout detect;
Watchdog timer;
Software reset;
UART break character detect reset.
For every reset source, there is a ag in the Reset Register, RSTSRC. The user can read
this register to determine the most recent reset source. These ag bits can be cleared in
software by writing a ‘0’ to the corresponding bit. More than one ag bit may be set:
During a power-on reset, both POF and BOF are set but the other ag bits are
cleared.
For any other reset, previously set ag bits that have not been cleared will remain set.
7.16.1 Reset vector
Following reset, the P89LPC9381 will fetch instructions from either address 0000H or the
Boot address. The Boot address is formed by using the Boot Vector as the high byte of the
address and the low byte of the address = 00H.
The Boot address will be used if a UART break reset occurs, or the non-volatile Boot
Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see
P89LPC9381
User’s Manual). Otherwise, instructions will be fetched from address 0000H.
7.17 Timers/counters 0 and 1
The P89LPC9381 has two general purpose counter/timers which are upward compatible
with the standard 80C51 Timer 0 and Timer 1. Both can be congured to operate either as
timers or event counter. An option to automatically toggle the T0 and/or T1 pins upon timer
overow has been added.
In the ‘Timer’ function, the register is incremented every machine cycle.
In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin, T0 or T1. In this function, the external input is sampled
once during every machine cycle.
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